Hi, I'm trying to simulate a Verilog file with many multi-dimensional arrays.
e.g. wire [31:0] bus[7:0]; It appears that these signals do not show up in the VCD file and thus can't be viewed in GTKWave. This was confirmed back in 2001 by Steve Williams. http://www.geda.seul.org/mailinglist/geda-dev44/msg00083.html Have there been any changes to iVerilog or GTKWave since 2001 to allow for easy viewing of these multi-dimensional arrays, without needing to instantiate new wires? It appears some tools like Modelsim and Aldec have implemented ways to do this. http://www.edaboard.com/ftopic148791.html Thanks, Denis Daly _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
