Tamas Szabo <[email protected]> writes:
> I would create a schematic symbol for AT91SAM7 device: 64 pins, lots > of them with multiplexed functions. > > 1. I can number pins round, 1 to 64 sequentially: > + easily fit to the schematic, 4x16 pin > + easy to create the symbol > - no functional grouping > - harder to understand the final schematic > - lots of crossing wires In my circuits the logic is mostly in the FPGA hdl, and the C-code inside the processor. The schematic is a preview of the pysical layout, so I can assign pins on the schematic level for routeability, grounding, and other physical considerations. So I prefer option 1. > 2. I can separate pins by functions, without keeping the pins' order: > + logically coherent signals can wire together > + nicer schematic, easy to understand > - harder to achieve suitable pinout Option 3.) I'd make a symbol for each function the chip supports, and instantiate a subset of those that I need, carefully annotating overlaps in pin usage, so that no pin is used twice accidentally. This is required work for using such a chip anyway. > Furthermore, since the above mentioned device has at least 3 function > for 32 pins, it is more difficult to setup a suitable pin placement > applying the second option. > However, since in my opinion schematic is a logical thing, I prefer > the second option. > > Which is the better solution? As you said, it's a matter of preference. -- Stephan _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
