And what will these subnets translate into in a layout tool? How
would that translation be handled in the net list? A net is a net in
my designs. If I have a "subnet" that I want handled differently
from the rest of the net, that is not something that is added to a
schematic because it is not related to the schematic. It is a layout
issue and I address it in layout. I may add some "documentation" to
the schematic in the form of notes, but they are just that, notes,
not design info that I expect to be conveyed in the netlist.
If I really want to designate portions of a net that need to be
separated by some PWB feature, I draw them as separate nets and then
connect them with a "part" that is used to connect them in the
layout. For example, I have a part which can use the same voltage
for I/Os that it uses for the core Vcc. But a different version of
the part uses a much lower core Vcc. So the two Vccs are separate
nets and I use a jumper symbol to connect them. In layout I have a
choice of how to implement that jumper, as a two pin header, a zero
ohm resistor or a two pin device that is nothing but a PWB copper
connection between the two pins.
How would you make use of "subnets" that would be useful that you
can't do with just nets?
Rick
At 01:34 PM 8/14/2010, you wrote:
On Sat, Aug 14, 2010 at 03:17:42AM -0400, Paul Tan wrote:
> ...In fact, I would like to see that gEDA can process ANY attributes
> attached to a net in similar fashion as it process ANY attributes
> attached to a symbol currently.
>
I agree, but I'm not sure this would be useful until we find a way
to split nets up into subnets - which is a much more complicated
change.
Otherwise, certain nets (such as power or ground nets), which often
have vastly different characteristics in different sections, would
be difficult to describe.
Andrew
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