The free FPGA compilers won't help much for an ASIC because they use
the internal structure of the FPGA when compiling VHDL or Verilog.
This doesn't exist on the ASIC.
Oliver
__________________________________________________________________
From: Peter Clifton <[email protected]>
To: gEDA user mailing list <[email protected]>
Sent: Fri, August 20, 2010 6:39:56 AM
Subject: Re: gEDA-user: the uber-scope (was: wishful UI)
On Fri, 2010-08-20 at 12:37 +0200, Armin Faltl wrote:
> VHDL - thats specs for a silicon compiler, right? - so you are using
> ASICs in
> "hobby"-project?
VHDL / Verilog is also used for developing with FPGAs.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)
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