Hi,
Thanks for the response. I was under the impression that Icarus was moving towards synthesis capability. I have the 0.8.1 Icraus version with me. I have made the source code compilable in Visual Studio 2005 though its not fully complete. May I know the reason as to why synthesis capability is being dropped ? I am really interested in making Icarus synthesizable. Here is my idea: I transform the Verilog code containing behavioral statements into verilog code that contains only gate level instantiations. This is passed as input to ABC Logic synthesis tool. Finally the output generated by ABC is passed to Versatile Place and Route(VPR) program which generates the bitstream. Regards, Ronald On 9/4/10, Stephen Williams <[1][email protected]> wrote: What are you trying to do? Are you really trying to "synthesize" your Verilog design, meaning you are trying to generate a bit stream to load into your FPGA? Or are you trying to compile and simulate your Verilog? Icarus Verilog is mostly a *simulator*, not a synthesizer. There were some synthesis capabilities back in the 0.8 release, but that support has been largely dropped in the 0.9 releases or current devel branch. Verilog code generator? OK, this suggests that you really are trying to *synthesize* (and not simulate) and no, not even the 0.8 release supported synthesis of user defined tasks. Ronald Mathias wrote: > Hi, > > > > I have written a verilog code that makes use of a user defined task to > do some computation. The task takes two parameters as input and one > parameter as output. > > > > When I try to synthesize it, I get the following error: > > > > internal error: NetProc::nex_output not implemented on object > type NetUTask > > internal error: NetProc::nex_output not implemented on object > type NetUTask > > Does this mean that icarus verilog has not yet support for synthesis of > user defined tasks? > > When I try to send the elaborated netlist to the verilog code generator > back end, the task definition is missing from the output. > > Is this a bug or the verilog code generator backend is still not > completely implemented ? > > Regards, > > Ronald -- Steve Williams "The woods are lovely, dark and deep. steve at [2]icarus.com But I have promises to keep, [3]http://www.icarus.com and lines to code before I sleep, [4]http://www.picturel.com And lines to code before I sleep." _______________________________________________ geda-user mailing list [5][email protected] [6]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:[email protected] 2. http://icarus.com/ 3. http://www.icarus.com/ 4. http://www.picturel.com/ 5. mailto:[email protected] 6. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
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