Hi all, We use Cadence Allegro at work, and how they implement keepouts may be interesting. There are several non-copper layers that are used to control the keep outs and keep-in. In this tool the keep in / keep out is related to how courtyards are defined.
Each library symbol (called a package in allegro) has a layer called place-boundary upon which a shape is drawn which defines it's courtyard. This can be a simple rectangle for an SMD component, or something more complex. This shape can have a height property. This defines a 3-D "No fly zone" for other components. You can have multiple shapes on this layer for one library part and they can have different height properties, including a clearance area above the board (I believe specified by a negative height). This allows constructs like "you can place a component here, as long as it is less than this tall. This is useful for odd components like a heatsink that overhangs part of the board. When placing components on the board, the shapes on this place-boundary layer (there is one for top and one for bottom) can not overlap. they can be adjacent but not overlap, unless the height of one of them fits under the minimum height of the other (the heatsink example above). This works well, but there is a downside in that the package to package spacing is defined in the library by the size of this shape on each part, but when you go to a high volume assembly house, they often have different rules as to how close some components can be. If their value is different than your . assumption, changing this value is not just a simple DRC rule change in the board, it has to be changed in the library. To do keepin / keep out there are special board layers called package keep in and package keep out (there are several of these layers, one for top, one for bottom, and one for all layers, you could generalize this to one per each layer if need be). On these layers you place outlines of the assorted regions you are trying to define. If any packages courtyard is even partially outside a package keepin layer, this is a DRC violation. If any packages courtyard is even partially inside a package keepout, this is also a violation. You can have multiple shapes on a package keep out layer, so there can be multiple regions you wish to keep parts out of. I believe you can also define a height property to these regions as well, so that you can have an area of the board for only components less tall than X, say under a shield can or under a heatsink. There are also analogous layers called route keepin and route keepout, which define where traces go and can not go. You can route a trace through a package keepout, under the assumption that the trace height wont cause a mechanical clearance issue. But a route keep out will prevent any traces from going through that area (good for an area where you remove soldermask for some reason). All traces (routes in allegro terminology) must be inside the route keepin. One way to use these is at the board edge. You may have an outline layer that defines the size of the board, but may wish a route-keepin shape that is say 20 mils inside the outline, to keep the traces away from the board edge, and a package keepin shape that is say 40 mils smaller, to keep components in from the edge. Incidentally the height property of the courtyard is often used by 3rd party 3D board rendering tools when a true 3d model of the component does not exist, the courtyard outline is extended upwards by the height property for a quick approximation of the 3D component. Regards, --Neil. _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
