Moin. When creating a multiple purpose HF connector footprint pcb refused to place vias close to each other. The trigger for refusal seems to be overlapping annulus. However, I see no strong hardware reason to second guess me where I want to put a via. As long as the holes themselves don't overlap, my fab is fine with it. If the hole is large enough they would even accept overlapping holes and probably use a milling bit to produce the irregularly shaped hole. pcbc not only ignored my wish to place a via. It silently dropped the "offending" vias from copy-paste action. In the end, I outsmarted the application by placing tiny vias and subsequently enlarged them to the desired size ;-)
If it were me, I'd rather do without this. "Please, don't interfere with my placement, no matter what. You may throw a warning at DRC if you have to." Would a patch to remove this feature, or at least make it dependent on the state of the enforce-DRC-clearance flag receive a welcome? ---<)kaimartin(>--- PS: Here is the offending footprint. http://www.gedasymbols.org/user/kai_martin_knaak/footprints/connector/HF_MULTI.fp -- Kai-Martin Knaak Öffentlicher PGP-Schlüssel: http://pgp.mit.edu:11371/pks/lookup?op=get&search=0x6C0B9F53 _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
