Kai-Martin Knaak <[email protected]> writes: > Does pcb complain if the user tries to overlap vias. Or does it just > silently refuse to put the via?
It does, and always has, printed a message to the message log. > Back then when I used protel we actually had cases where overlapping > were holes deliberate. The hole had to be non-round and clad with metal. Right. That's why we need to preserve these "cheats" once the user gets them into the pcb file. _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
