Rick Collins wrote: > With the hierarchical ref des it tells you which > instance. With component renumbering you have to search to find the > right sheet... the same as non-hierarchical schematics.
If the refdes of a resistor in the layout reads "3R12" I know it is on page 3 of my schematics printout. > There is more than one way to view instantiation. You don't have to > "see" it as the exact same, single sheet. If you do, there is no > way to have your documentation in step with the actual board > produced... It sure is in step. The hierarchy of schematic is just not flattened out. > The way you are viewing subsheets, they are macros and > the schematic is a programming language. In a way, this is always the case, even with a flat schematic. Symbols get mapped to footprints according to some rules. E.g, symbols with the same refdes are all part of the same component. > A schematic is intended to > be documentation and each page has to show the ref des that appears > on the final product. Whether or not this is desirable depends on the work-flow and on the project. Remember the 69 instants of a sub circuit I mentioned? This is a real world example. It would not help in any way, if I had this sub circuit printed 69 times. > The only fly in the ointment is back annotation. ack. I got the impression that refdes renaming due to hierarchical design is the road block that prevents back annotation in geda/pcb. ---<)kaimartin(>--- -- Kai-Martin Knaak Öffentlicher PGP-Schlüssel: http://pgp.mit.edu:11371/pks/lookup?op=get&search=0x6C0B9F53 _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
