Peter Clifton <[email protected]> writes: > On Mon, 2011-01-24 at 07:48 -0800, Ouabache Designworks wrote: >> The special symbols is supposed to fuse netnames as issued on the >> netlist, >> not labels on the schematic. >> ------------------------------------------- >> If you are also fusing the copper on the board then I would kind of >> like to see that when I am viewing the schematic. >> You want to give the user a choice. If I pull up a component view then >> I want to see the signal names from the original designer. If I am >> traversing a hierarchy and open an instance view then I want to see the >> signal names that match the names in the parent instance. >> John Eaton > > For a loop antenna, for example, the solution needs to be in PCB.. allow > footprints / "functional groups" which implement RF components by > placing copper on some layer. > > For me, this raises a very interesting design question: > > How do I go from abstract inductor / transmission line / (capacitance > even?) representations on a schematic, to correctly DRC'd board layout?
This will probably require an additional tool. The tool needs to extract the properties of the wiring from the layout via some techology file that describes the properties of the board materials (layer stack, etc). The schematic will have attributes on nets that spec what to check for. IMHO, net segments should be explicitly marked with the short-symbol that was discussed. A gnetlist backend will provide a netlist to the verification tool that includes the attributes and net segments. The PCB gnetlist backend merges the net segments. How to split out the net segments during extraction is probably not easy. > The inductor will end up as a shaped piece of copper tracking, and at > this point, you realise that "net" is a very DC term! The inductor could be a subschematic with shorted pins via two short symbols, with a net in between that asks for an inductance check of some sort. > We would need to have some way to demarcate the start and end of the > inductor in PCB, or to draw it on a layer, or with an attribute which > causes the copper making up the "component" to be disjoint from either > net connecting to that section. That piece of board layout becomes a > "component", not an interconnect between components. The DRC could be told to treat certain layers in a group as component copper. > One might imagine a similar method being useful to join two > hierarchically shorted nets together... have a "link" component which > joins AGND and DGND, which is implemented by copper drawn on the board > between those two power planes. > > This would then allow preservation of important DRC checks such as > making sure the correct plane / return path is used for signals. > > Regards, -- Stephan _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
