On 06/06/2011 01:13 PM, Ethan Swint wrote:
OK- I've been messing around with hierarchy for the first time, but I'm a bit lost. I've got an asymmetric phase leg inverter with three phases,
Yes, that's a good use of the flattened hierarchy we can do for now.
My problem then comes when I try to create the PCB. Components there take on the refdes "A/D?", as opposed to "A/D1", "A/D2", etc. I did run across http://www.bourbonstreetsoftware.com/GEDABlocks.html, but I was hoping to find something a bit more automatic. My Bing-fu and Google-fu have failed me, as well. My gnetlistrc file consists of: (hierarchy-netattrib-mangle "disabled") (hierarchy-netname-mangle "disabled") (hierarchy-uref-mangle "disabled") What obvious thing (or reference material) am I missing?
In a design where I used multiple layout zones I did not have those in gnetlistrc, but you might need lines like these: (source-library ".") (source-library "../tmote-flat-connect_") (source-library "../tmote-revb_") to pull in any subschematics John _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
