oops, I left an annoying error in the SIL definition that effected pins
above 3 ;)
Eric Winsor wrote:
>
<snip>
This parenthesis should be gone alone with its counterpart.
> ifelse(eval($4 > 3), 1, `(
-----------------------------------^
> forloop(`i', 1, eval($4 /2 -1),
> `ElementLine(0 eval(i * 200) 100 eval(i * 200) 10)
> ')
> )')
----------^
Correction follows:
# -------------------------------------------------------------------
# Added ifelse to check for number of pins greater than 3
# This stops an infinite loop from occurring for pins < 4.
# Eric Winsor and Chris Ellec 1 July 2002
# the definition of a SIL package without a common pin
# $1: canonical name
# $2: name on PCB
# $3: value
# $4: number of pins
define(`PKG_SIL',
`define(`MAXY', `eval(`$4' * 100 -50)')
Element(0x00 "$1" "$2" "$3" 160 10 3 100 0x00)
(
forloop(`i', 1, $4,
`PIN(50, eval(i * 100 -50), 50, 20, i)
')
ElementLine( 0 50 0 MAXY 20)
ElementLine(100 50 100 MAXY 20)
ElementArc(50 50 50 50 180 180 20)
ElementArc(50 MAXY 50 50 0 180 20)
ifelse(eval($4 > 3), 1, `
forloop(`i', 1, eval($4 /2 -1),
`ElementLine(0 eval(i * 200) 100 eval(i * 200) 10)
')
')
Mark(50 50)
)')
--
Eric Winsor
Stewart Radiance Laboratory
Space Dynamics Laboratory - USURF
Bedford, MA 01730
