I've only used a for inside a begin end block and after a @negedge or @posedge statement. You need to think of verilog as "all in parallel", and only throw a few procedural parts into places between clocks for compactnes of code only! Here, your purpose is to generate a pattern of data that, in hardware, will translate to an output data pattern transitioning jsut after @posedge(Clk).... You use words like test, perhaps you really want to be using a test language external to verilog that is more procedural. Jeda is something to look into. It is supposed to work with iverilog, but last I tried it had snags running on my debian woody distro.
John Griessen On Wed, 2003-01-22 at 00:34, Brendan J Simon wrote: > > I get a compile error if I try the following in a test harness. Is it > an Icarus bug or a Verilog limitation ??? > > integer i; > for (i = 0; i < 64; i = i + 8) begin > @posedge(clk) > data = test[i:(i+8)]; > end >
