[EMAIL PROTECTED] said: > I am studying the use of Icarus Verilog to create an RTL netlist. From > that netlist, which has INV, OR, NAND, etc defined, I am trying to > understand how to flow the netlist into Magic.
The best way to get from Verilog to MAGIC is to write a code generator that generates the appropriate netlist format. The ivl_target API actually communicates the compiled design with LPM (approximately) level devices, which the code generators then write into real world netlist/library combinations. The newer -tfpga supports Xilinx Virtex parts more directly then the -txnf code generator you are apparently using. The EDIF that comes out of that code generator can be handed directly to the Xilinx tools for map/par. The sqrt-virtex.v example demonstrates this. ASIC based libraries are different from FPGA parts libraries, so hacking the -tfpga code generator would not be ideal. It would be fairly nifty if someone would like to take the time to write a code generator for the libraries supported by MOSIS. Writing a code generator is easier then writing a synthesizer (the synthesis is already done) and even easier then writing the design for your chip; but harder then writing a simple set of printfs. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."
