I'm wondering if anyone saw my last message relating to Verilog and how to model a three-state bus in Icarus?your issues were not icarus related - just verilog.
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Samuel A. Falvo II
in general, tristate busses within a chip are in my opinion evil and should be avoided.
If you have to do this, I'd suggest you use a wrapper that separates the bus into 2 directions, and
just resolve the busses there, once.
I suspect you also need to review the difference between wires and registers,
from your example.
john
