for me, iverilog delay and SDF backannotation processing is not quite there yet at gate level.
Does a great job with RTL though.
john
Laurin Blacken wrote:
This may have already been reported as a bug, but I'll send this in just in case.
I'm trying to simulate a placed and routed xilinx design from which the xilinx tool has generated a gate level module.
Iverilog is having trouble with the xilinx sim primitives that get instantiated..
iverilog -y /usr/local/xilinx/verilog/src/simprims zsimtest.v
/usr/local/xilinx/verilog/src/simprims/X_TRI.v:17: warning: choosing typ expression.
/usr/local/xilinx/verilog/src/simprims/X_TRI.v:17: warning: choosing typ expression.
/usr/local/xilinx/verilog/src/simprims/X_TRI.v:18: warning: choosing typ expression.
/usr/local/xilinx/verilog/src/simprims/X_TRI.v:18: warning: choosing typ expression.
/usr/local/xilinx/verilog/src/simprims/X_TRI.v:19: warning: choosing typ expression.
/usr/local/xilinx/verilog/src/simprims/X_TRI.v:19: warning: choosing typ expression.
/usr/local/xilinx/verilog/src/simprims/X_TRI.v:20: warning: choosing typ expression.
/usr/local/xilinx/verilog/src/simprims/X_TRI.v:20: warning: choosing typ expression.
/usr/local/xilinx/verilog/src/simprims/X_INV.v:17: warning: choosing typ expression.
/usr/local/xilinx/verilog/src/simprims/X_INV.v:17: warning: choosing typ expression.
/usr/local/xilinx/verilog/src/simprims/X_FF.v:37: parse error
/usr/local/xilinx/verilog/src/simprims/X_FF.v:31: error: syntax error in specify block
zsimtest.v:14: error: Unable to bind wire/reg/memory `ztest' in `zsimtest'
1 error(s) during elaboration.
...
It appears to me that there is a problem with the specify block?
I've got icarus running on 3 different platforms: RH Linux, Cygwin and Mac OSX -same thing on all three.
My goal is to simulate the gate level fpga module with back-annotated sdf info.
I can send the .v files for the simprims in question if you don't already have them. I can send the gate level module and tbench if you think that would be necessary.
Is it something I'm doing or is it a bug? Is there a work around?
Laurin Blacken
