- somehow steal the implementation that synthesizes "wire try1 = (state_en == 5'd8)" into gates, or
- add code that generates valid EDIF netlist elements for LPM_COMPARE
I'm sure Stephen has an opinion about which is the Right Thing to do. I'm also curious to know why sometimes the comparison gets synthesized and other times it's handed off for output as a module.
On Mon, 2004-10-11 at 23:53, Ming Deng wrote:
It seems to me that continuous assignment in "wire" statement
wire try1 = (state_en == 5'd8);
is tended to be compiled into BUF, INV and AND gates while procedural
assignment
out<=(in==5'b00101);
or "if" statement in procedure
if (state_en == 5'b11111) begin
are tended to be compiled into LPM_COMPARE and LPM_CONSTANT devices. But
unfortunately most LPM_COMPARE devices have not been implemented yet.
Ming Deng
Stephen Williams wrote:
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> Ming Deng wrote:
> | I ran the sample file on Icarus Verilog 0.7, got the same result.
> |
> | After taking a briefly look into the code, I found there were no any
> | comparators implemented for fpga-lpm. See the following snippet from
> | tgt-fpga/d-lpm.c
>
> The -tfpga -parch=virtex supports more stuff then the default
> LPM family. It's simply a matter of filling in the table that
> you discovered in the d-lpm.c source file.
>
> - --
> Steve Williams "The woods are lovely, dark and deep.
> steve at icarus.com But I have promises to keep,
> http://www.icarus.com and lines to code before I sleep,
> http://www.picturel.com And lines to code before I sleep."
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