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-- Cut here -- From: "Thomas A.D. Riley" <[EMAIL PROTECTED]> I am trying out the fpga target to look at edif netlists (not really for FPGAs). I tried a simple test chunk of code FIRcontroller.v which simulates OK. when I try: iverilog -o thingy.edif -tfpga FIRcontroller.v I get an edif netlist but I suspect it is wrong because I also get: fpga.tgt: IVL_LPM_CMP_EQ not supported by this target. fpga.tgt: IVL_LPM_CMP_EQ not supported by this target. Although the error messages don't say where the problem occurs, I suspect it might have something to do with the following two ines wire try1 = (state_en == 5'd8); wire try2 = (state_en == 5'b11111); Does any one have an explanation or a work around? Tom Riley Kaben Research Inc. tel: (613) 826 6649 xtn. 112 fax: (613) 826 6650 mobile: (613) 797 7774 mobile in Europe : 011 358 40 818 4066 http://www.kabenresearch.com
