> > > Moving forward, it would be best if PCB didn't hardcode the concept of > > layer type into specific layers. Rather, you should just define > > whether the layer is silk, mask, or metal, and additionally define > > whether it is positive or negative. > > That is a very BAD idea. PCB is not a drawing tool; it understands things > like design rules, connectivity etc. It makes no sense to have software to > trace connectivity on the silk, mask, keepout, etc layers or to not be able > to understand that metal layer DRCs are different from the silk layer, or to > deal with elements having various "grouped" metal, mask, and silk features > if all layers were arbitrary.
Yeah, I agree. I wasn't focussed on thinking while writing this particular paragraph. I *do* think a built-in stack-up like that which I suggested: silk_top (pos) mask_top (neg) paste_top (neg) metal_top (pos or neg) int2 (pos or neg) int3 (pos or neg) etc. . . . metal_bot (pos or neg) paste_bot (neg) mask_bot (neg) silk_bot (pos) Assembly (pos) (perhaps have top and bottom?) Board outline (or just consolidate with Assy layer?) Drill makes sense. Then, the program will know that if I put a pad on teh top layer, it will put the right metal_top rectangle down, cut the right void in mask_top & paste_top, and so on. It will also know that if I place a via, it should connect to the metal layers where connectivity is present, void the layers where connectivity is absent, and not void out the mask, unless the via is a test via. The prog would also have the notion of various DRCs built into it. I agree that the layers can't be aribtrary, because that would make building the DRC checking and connectivity & mfg rule awareness difficult. OTOH, I don't like the current layer arrangement in PCB, which provides separate tabs for metal_top and GND_top (i.e. plane), and so on. There should be one tab per layer & you should handle plane vs. routing layer issues using positive and negative layers. Stuart > > h. > > >
