People, I'm trying to use Icarus Verilog for some chip generation I'm doing. That package seems to be working fine, but trying to generate a netlist using gnetlist -g verilog ---- on a schematic which used vector notation on signals seems to generate multiple declarations of the vectored input and output signals without the vector reference. Is this a common problem, or am I doing something wrong?
As far as I can tell, scaler signal references netlist OK.
Harold Skank
