I have a question about edif net format; I came across this when I was running Icarus Verilog. If this is not the right forum for this, kindly point me at the right direction.
Is it legal in edif to have multiple net refereces for parts of the same net? For example, can the net below (net N16 (joined (portRef I1 (instanceRef U29)) (portRef Y (instanceRef U23)) (portRef I0 (instanceRef U27)) )) be represented by two nets, with a common point: (net N16 (joined (portRef I1 (instanceRef U29)) (portRef Y (instanceRef U23)) )) (net N161 (joined (portRef I1 (instanceRef U29)) (portRef I0 (instanceRef U27)) )) Cordially, CN
