Hi,
The following is a simplified artifical testcase (extracted from the standard
prep3.v test bench, I posted a few days ago).
============
module multiAssign ( in, out) ;
input in ;
output out ;
reg out ;
reg s;
always @ (in)
begin
out = 0; //default
case (s)
0: out =1;
1: out =0;
endcase
end
endmodule
============
This produces a netlist with two ouputs connected together on out.
BTW, if I move the out=0; //default to inside the case, as default: out=0; the
problem goes away. But, some people here claim that this is a fairly common
practice to have the default before the case.
Is this a known problem in ivl synthesis? Is this easy to fix?
Cordially, CN
