Hello.
Am 27.09.2005 08:17:10 schrieb(en) Samuel A. Falvo II:
> It has always baffled me how Verilog
> simulators seem to be literally everywhere, but if OpenCores is any
> indication, ALL the truely interesting designs are VHDL.
If done the job to count all ready-to-use designs on OpenCores.org
ready-to-use VHDL Verilog
------------------------------------------------
Arithmetic cores 3 -
Prototyping boards 2 -
Communication controller 8 8
Coprocessors - 1
Crypto cores 2 5
ECC cores 1 1
Library 2 -
Microprozessors 9 1
Others 4 6
SoC 4 3
System controller - 3
Video controller - 1
------------------------
35 29 in summa: 65
54,7% 45,3%
all designs VHDL Verilog
------------------------------------------------
Arithmetic cores 3 -
Prototyping boards 3 2
Communication controller 15 12
Coprocessors - 1
Crypto cores 4 6
ECC cores 2 3
Library 2 -
Microprozessors 14 9
Others 9 8
SoC 6 3
System controller 1 3
Video controller - 2
------------------------
59 49 in summa: 108
54,7% 45,3%
Well, in both tables the same picture we see. There are some more designs
(54,7%) in VHDL than in Verilog (45,3%) -the same values (in %) for booth
tables aren't a mistake- !
We have to deal with *both* languages like everywhere in our practice. Both
languages have pros and cons, but we *can't* say "ALL the truely interesting
designs are VHDL". That's a completly subjective point-of-view. What the guy
says who needs crypto or ECC cores?
Welcome to variety :-)
