On Tue, Oct 11, 2005 at 04:02:37AM -0400, [EMAIL PROTECTED] wrote: > > > I bumped the ball size down from the Xilinx recomended 0.4mm to 0.34mm, > > > and everything worked out fine. > > In our experience, bumping down pad size can be a dangerous thing. I'd be > carefull and test a few before I had that many made. The issue is not whether > you can attach a bga device to down sized pads, but if it will stay attached > through time. In essence, I am suggesting that down sizing the pad can > emulate bad printing, device warpage and/or PCB warpage. Printing is talked > about here: > > http://www.aimsolder.com/techarticles/tech sheet BGA voiding- reducing > through > process optimization.pdf > > The rest is talked about here: > > http://www.akrometrix.com/pdf/Tech_Papers/CSP Board Level Reliability.pdf > > > Best regards > > Marvin
That was just for the prototype. I intend to use a manufacturer who can do smaller vias for production to allow full size pads. I would never sell something with a hack like that. -- Darrell Harmon http://dlharmon.com/dspcard Credit card size DSP/FPGA board
