Larry Doolittle wrote:
Friends -
On Fri, Nov 11, 2005 at 01:03:03PM -0800, Larry Doolittle wrote:
I took a whack at laying out a Xilinx Spartan3-FT256 in PCB.
I posted my results so far at
http://recycle.lbl.gov/~ldoolitt/ft256/
I just updated that page, based in part on the comments
posted here. Thanks to all who replied!
The page now also references Darrell Harmon's DSPCARD,
and contrasts the two board designs.
Greg Bengeult commented on my decoupling question:
Xilinx has an app note on their web site (XAPP623) that addresses the
decoupling issue for any chip, not a specific type or package. It's
written for engineers and can be a long and dry read, but all of the
important information is in there.
I have read that note ages ago, and re-read it just now. It is too
general to answer specific questions about the Spartan3. The closest
it comes is where it asserts
The FPGA package and the PDS inside it are very carefully sized
to meet the needs of a fully utilized die without being overly
conservative. The number of VCC and GND pins on a package for a
given device is determined based on the needs of a 100% utilized
FPGA.
That gives an inside peek into the mind-set of Xilinx package
designers. So this is _almost_ a guarantee that 1 (properly laid
out) cap per pin is enough.
I welcome constructive criticism, especially in the
context of (relatively) high speed design. My interest
in this chip is for designs running at about 100 MHz.
Still, of course.
- Larry
IMHO, you just can't get enough storage in a cap to supply the
instantaneous switching needs of a high speed IC. Generally, this comes
from the power planes themselves. If you can get your power and ground
plane to within 0.002" of each other (pretty realistic these days), you
will make the best capacitor possible. That doesn't mean you can skimp
on bulk capacitance, but remember it's the plane that supplies power for
the switching edges first. BTW, those long inductive traces you had
there for power will kill your chip at high frequency.
One other point, something I noticed with the way you escaped your BGA.
Each ball has a short trace that aims inward toward the center of the
chip. In my experience, it usually goes outward. The benefit is a
larger routing area in the center of the BGA. You get a "+" looking
space, but if you aim you escapes inwards, the "+" is really thin.
Oh, your 6 layer board is not symmetrical. Check with your PCB vendor
to see if it'll warp.
