On Thu, Jan 05, 2006 at 01:27:56AM -0500, DJ Delorie wrote: > > > Ok, one of the drc tests, apparently, is to test if a land pattern > > conforms to the design rules (e.g. silk screen thickness) why doesn't > > the drc run every time a land pattern is dropped into a layout? Is it > > not better to be proactive then reactive? > > I hope by the time you've got an element in your library it's passed > some sort of QA. However, my previous comment fits here too - the DRC
The elements in the library are usual for precision class 5, 6, or 7 and my precision class is 4 (0.35mm line/0.30mm gap). The fact that the element passed a QA doesn't mean that it will be correct in the board because the QA could have been done for a different precision class than what the board is being designed for. > parameters may change over time. I can see a need to switch to more > restrictive DRCs for cost savings, or globally "ease off" if a looser > DRC is selected. The first needs the fix-on-the-fly solution, the > second needs the global change option. You might not even know the > DRC parameters until late in the design. If you learn DRC parameter late, you usually end up with necessity to rip up 1/2 of the tracks and place them again (until you are performing a board space wasting contest). > For silkscreen on dense boards, line thickness might not even be a > design consideration. You'd just set it to as thin as the fab house > allows just before you send it out. > > Note that PCB does have restrictions on where you can put vias; it > won't let them overlap for example. There are *some* drc-on-the-fly > features built in, it's just not 100% coverage. These DRC restrictions must be turned off anyway because they are broken and often don't even allow you to connect two points connected with a ratnest. CL<
