OK, maybe I'm being brain dead, but I'm reading that you're either not
answering the question, or you're telling me conflicting information.
I'm probably wrong on both counts, but I'm not seeing your point.
You tell me that I must have each gschem element represented by a
footprint. But you tell me that having individual logic gates makes the
schematic easier to read.
I wholly concur with the second half, but there is no "footprint" for
each individual logic gate. Since you have also told me that since each
logic gate must have its own footprint, I take that to mean by
implication that I cannot use the individual logic gates, but must
instead use a symbol that resembles an actual 7400 chip.
Can you clear up whatever it is I am missing from your replies?
Thanks!
David Logan
John Luciani wrote:
Separating the 7400 into four gates (slots) usually makes for a more
readable schematic.
You have more space to place each gate and its peripheral components in
a logical arrangement.
(* jcl *)
