Hello:
I am having some problems getting the waveform from the
vcd output of a simulation. This is the simple verilog
file with my test simulation:
=======================================================
module this;
reg clk1,clk2;
initial
begin
#0
clk1 = 0;
clk2 = 1;
#40;
$finish;
end
always begin
#2 clk1 = ~clk1;
#4 clk2 = ~clk2;
end
initial
begin
$dumpfile("this.vcd");
$dumpvars;
end
endmodule
=============================================================
I compile this with iverilog this.v
I then run it by doing vvp a.out
Which gives me a 'dumpfile this.vcd opened for output'
I do get a dump file (this.vcd), which has the following
contents:
=============================================================
$date
Tue May 23 18:33:03 2006
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module this $end
$var reg 1 ! clk1 $end
$var reg 1 " clk2 $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
1"
0!
$end
#2
1!
#6
0"
#8
0!
#12
1"
#14
1!
#18
0"
#20
0!
#24
1"
#26
1!
#30
0"
#32
0!
#36
1"
#38
1!
============================================================
The iverilog is version 0.8
The gtkwave is version is 1.3.81
Looking at the above output, it appears that all of the
varialbe information is there.
The graph on the gtkwave only shows the time. I don't see
any of the variables.
I appreciate any help.
Thank you
Mark Allyn
