Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/7961 )
Change subject: arch-arm: Handle route to EL2 in Supervisor Trap
......................................................................
arch-arm: Handle route to EL2 in Supervisor Trap
Supervisor Trap is supposed to be able to handle exceptions routed
to EL2, which is enabled by HCR_EL2.TGE. This fix adds routeToHyp()
function to Supervisor Trap to handle this, similar to that in
UndefinedFault, DataAbort, etc.
Change-Id: I1fcf9f2d445ecbc13c8f6d3b7d599728b0250ab7
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7961
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
2 files changed, 32 insertions(+), 3 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index d143056..27894e0 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2014, 2016-2017 ARM Limited
+ * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -923,10 +923,37 @@
return (from64 ? EC_SMC_64 : vals.ec);
}
+bool
+SupervisorTrap::routeToHyp(ThreadContext *tc) const
+{
+ bool toHyp = false;
+
+ SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
+ HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+ CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
+
+ // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
+ toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0);
+ return toHyp;
+}
+
+uint32_t
+SupervisorTrap::iss() const
+{
+ // If SupervisorTrap is routed to hypervisor, iss field is 0.
+ if (hypRouted) {
+ return 0;
+ }
+ return issRaw;
+}
+
ExceptionClass
SupervisorTrap::ec(ThreadContext *tc) const
{
- return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
+ if (hypRouted)
+ return EC_UNKNOWN;
+ else
+ return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
}
ExceptionClass
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index fa6740a..bec2c0e 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2013, 2016-2017 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2016-2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -335,6 +335,8 @@
overrideEc(_overrideEc)
{}
+ bool routeToHyp(ThreadContext *tc) const override;
+ uint32_t iss() const override;
ExceptionClass ec(ThreadContext *tc) const override;
};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I1fcf9f2d445ecbc13c8f6d3b7d599728b0250ab7
Gerrit-Change-Number: 7961
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
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