Robert Scheffel has uploaded this change for review. ( https://gem5-review.googlesource.com/9821


Change subject: arch-riscv: jump to trap vector on fault
......................................................................

arch-riscv: jump to trap vector on fault

This patch extends the basic fault support in disabling interrupts
globally in the mstatus register. Other bits in mstatus are set
according to the specification.
Afterwards the pc is set to an address stored in the mtvec register.

Change-Id: I30b2fcaf96697e6345d4308d91d4d5b49cb042b1
---
M src/arch/riscv/faults.cc
M src/arch/riscv/registers.hh
2 files changed, 81 insertions(+), 4 deletions(-)



diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index ce50149..1ea2036 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -51,7 +51,10 @@
         panic("Full system mode not supported for RISC-V.");
         MiscRegIndex cause = MISCREG_MCAUSE;
         MiscRegIndex epc = MISCREG_MEPC;
-        MISCREG prv = 0x3;
+        MiscReg prv = 0x3;
+        MiscReg pp = tc->readMiscRegNoEffect(MISCREG_PRV);
+        MSTATUS status = tc->readMiscReg(MISCREG_MSTATUS);
+
         if (bits(tc->readMiscReg(MISCREG_PRV), 1) == 0
             && bits(tc->readMiscReg(MISCREG_MEDELEG), _code) != 0) {
             cause = MISCREG_SCAUSE;
@@ -64,11 +67,20 @@
             epc = MISCREG_UEPC;
             prv = 0x0;
         }
-        tc->writeMiscReg(cause,
+        tc->setMiscReg(cause,
(_interrupt << (sizeof(MiscReg) * 4 - 1)) | _code);
-        tc->writeMiscReg(epc, tc->instAddr());
-        tc->writeMiscReg(MISCREG_PRV, prv);
+        tc->setMiscReg(epc, tc->instAddr());
+        tc->setMiscReg(MISCREG_PRV, prv);

+        // disable interrupts
+        status.mpp = bits(pp, 1, 0);
+        status.mpie = status.mie;
+        status.mie = 0;
+        tc->setMiscReg(MISCREG_MSTATUS, status);
+
+        PCState pc;
+        pc = tc->readMiscReg(MISCREG_MTVEC);
+        tc->pcState(pc);
     } else {
         invoke_se(tc, inst);
         PCState pcState = tc->pcState();
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 121c909..0dc49a4 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -429,6 +429,71 @@
     {MISCREG_DSCRATCH, "dscratch"}
 };

+BitUnion64(MSTATUS)
+    Bitfield<63>        sd;
+    Bitfield<35, 34>    sxl;
+    Bitfield<33, 32>    uxl;
+    Bitfield<22>        tsr;
+    Bitfield<21>        tw;
+    Bitfield<20>        tvm;
+    Bitfield<19>        mxr;
+    Bitfield<18>        sum;
+    Bitfield<17>        mprv;
+    Bitfield<16, 15>    xs;
+    Bitfield<14, 13>    fs;
+    Bitfield<12, 11>    mpp;
+    Bitfield<8>         spp;
+    Bitfield<7>         mpie;
+    Bitfield<5>         spie;
+    Bitfield<4>         upie;
+    Bitfield<3>         mie;
+    Bitfield<1>         sie;
+    Bitfield<0>         uie;
+EndBitUnion(MSTATUS)
+
+BitUnion64(SSTATUS)
+    Bitfield<63>        sd;
+    Bitfield<33, 32>    uxl;
+    Bitfield<19>        mxr;
+    Bitfield<18>        sum;
+    Bitfield<16, 15>    xs;
+    Bitfield<14, 13>    fs;
+    Bitfield<8>         spp;
+    Bitfield<5>         spie;
+    Bitfield<4>         upie;
+    Bitfield<1>         sie;
+    Bitfield<0>         uie;
+EndBitUnion(SSTATUS)
+
+BitUnion64(USTATUS)
+    Bitfield<4>         upie;
+    Bitfield<0>         uie;
+EndBitUnion(USTATUS)
+
+BitUnion64(MIP)
+    Bitfield<11>        meip;
+    Bitfield<9>         seip;
+    Bitfield<9>         ueip;
+    Bitfield<7>         mtip;
+    Bitfield<5>         stip;
+    Bitfield<4>         utip;
+    Bitfield<3>         msip;
+    Bitfield<1>         ssip;
+    Bitfield<0>         usip;
+EndBitUnion(MIP)
+
+BitUnion64(MIE)
+    Bitfield<11>        meie;
+    Bitfield<9>         seie;
+    Bitfield<9>         ueie;
+    Bitfield<7>         mtie;
+    Bitfield<5>         stie;
+    Bitfield<4>         utie;
+    Bitfield<3>         msie;
+    Bitfield<1>         ssie;
+    Bitfield<0>         usie;
+EndBitUnion(MIE)
+
 }

 #endif // __ARCH_RISCV_REGISTERS_HH__

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I30b2fcaf96697e6345d4308d91d4d5b49cb042b1
Gerrit-Change-Number: 9821
Gerrit-PatchSet: 1
Gerrit-Owner: Robert Scheffel <robert.scheff...@tu-dresden.de>
Gerrit-MessageType: newchange
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