Daniel Carvalho has uploaded this change for review. ( https://gem5-review.googlesource.com/9825

Change subject: mem-cache: Make block whenReady private
......................................................................

mem-cache: Make block whenReady private

Having different derived block caches is difficult due to the
fact that all its members are public.

whenReady has been modified to private, and its corresponding
setter and getter have been created.

Change-Id: I9d19fa1a0f8b7088a1707cf5f3c0988873d8d17e
---
M src/mem/cache/blk.hh
M src/mem/cache/cache.cc
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/fa_lru.cc
4 files changed, 38 insertions(+), 16 deletions(-)



diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index 14ab652..3050efa 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -95,6 +95,9 @@
     /** Data block tag value. */
     Addr _tag;

+    /** Which curTick() will this block be accessible. */
+    Tick _whenReady;
+
   public:
     /**
* Contains a copy of the data in this block for easy access. This is used
@@ -105,9 +108,6 @@
      */
     uint8_t *data;

-    /** Which curTick() will this block be accessible */
-    Tick whenReady;
-
     /**
      * The set and way this block belongs to.
      * @todo Move this into subclasses when we fix CacheTags to use them.
@@ -230,7 +230,7 @@
         _status = 0;
         _taskID = ContextSwitchTaskId::Unknown;
         _srcMasterID = Request::invldMasterId;
-        whenReady = MaxTick;
+        _whenReady = MaxTick;
         isTouched = false;
         refCount = 0;
         tickInserted = MaxTick;
@@ -351,6 +351,26 @@
     }

     /**
+     * Set the curTick() on which this block will be accessible.
+     *
+     * @param whenReady The tick on which this block will be accessible.
+     */
+    void setWhenReady(const Tick whenReady)
+    {
+        _whenReady = whenReady;
+    }
+
+    /**
+     * Get the curTick() on which this block will be accessible.
+     *
+     * @return The tick on which this block will be accessible.
+     */
+    Tick whenReady() const
+    {
+        return _whenReady;
+    }
+
+    /**
      * Track the fact that a local locked was issued to the
      * block. Invalidate any previous LL to the same address.
      */
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 36da062..68a6e48 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -420,8 +420,8 @@
         DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
         incHitCount(pkt);
         // populate the time when the block will be ready to access.
-        blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
-            pkt->payloadDelay;
+        blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay +
+            pkt->payloadDelay);
         return true;
     } else if (pkt->cmd == MemCmd::CleanEvict) {
         if (blk != nullptr) {
@@ -482,8 +482,8 @@

         incHitCount(pkt);
         // populate the time when the block will be ready to access.
-        blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
-            pkt->payloadDelay;
+        blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay +
+            pkt->payloadDelay);
         // if this a write-through packet it will be sent to cache
         // below
         return !pkt->writeThrough();
@@ -1971,8 +1971,8 @@
         pkt->writeDataToBlock(blk->data, blkSize);
     }
     // We pay for fillLatency here.
-    blk->whenReady = clockEdge() + fillLatency * clockPeriod() +
-        pkt->payloadDelay;
+    blk->setWhenReady(clockEdge() + fillLatency * clockPeriod() +
+        pkt->payloadDelay);

     return blk;
 }
diff --git a/src/mem/cache/tags/base_set_assoc.hh b/src/mem/cache/tags/base_set_assoc.hh
index 524cb68..83bf6c9 100644
--- a/src/mem/cache/tags/base_set_assoc.hh
+++ b/src/mem/cache/tags/base_set_assoc.hh
@@ -158,10 +158,11 @@
             lat = accessLatency;
             // Check if the block to be accessed is available. If not,
             // apply the accessLatency on top of block->whenReady.
-            if (blk->whenReady > curTick() &&
-                cache->ticksToCycles(blk->whenReady - curTick()) >
+            Tick whenReady = blk->whenReady();
+            if (whenReady > curTick() &&
+                cache->ticksToCycles(whenReady - curTick()) >
                 accessLatency) {
-                lat = cache->ticksToCycles(blk->whenReady - curTick()) +
+                lat = cache->ticksToCycles(whenReady - curTick()) +
                 accessLatency;
             }

diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc
index a5f5592..5537370 100644
--- a/src/mem/cache/tags/fa_lru.cc
+++ b/src/mem/cache/tags/fa_lru.cc
@@ -190,10 +190,11 @@
         lat = accessLatency;
         // Check if the block to be accessed is available. If not,
         // apply the accessLatency on top of block->whenReady.
-        if (blk->whenReady > curTick() &&
-            cache->ticksToCycles(blk->whenReady - curTick()) >
+        Tick whenReady = blk->whenReady();
+        if (whenReady > curTick() &&
+            cache->ticksToCycles(whenReady - curTick()) >
             accessLatency) {
-            lat = cache->ticksToCycles(blk->whenReady - curTick()) +
+            lat = cache->ticksToCycles(whenReady - curTick()) +
             accessLatency;
         }
         assert(blk->getTag() == tag);

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I9d19fa1a0f8b7088a1707cf5f3c0988873d8d17e
Gerrit-Change-Number: 9825
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho <oda...@yahoo.com.br>
Gerrit-MessageType: newchange
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