Tiago Mück has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18414 )
Change subject: mem-ruby: Cache latencies for MOESI_CMP_dir
......................................................................
mem-ruby: Cache latencies for MOESI_CMP_dir
Modified both L1 and L2 controllers to take into account the cache
latency parameters. Default values in the configuration script updated
as well.
Change-Id: I72bb8dd29ee0b02da06e1addf13b266fe4d1e979
Signed-off-by: Tiago Muck <tiago.m...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18414
Tested-by: kokoro <noreply+kok...@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
Maintainer: Jason Lowe-Power <ja...@lowepower.com>
---
M configs/ruby/MOESI_CMP_directory.py
M src/mem/protocol/MOESI_CMP_directory-L1cache.sm
M src/mem/protocol/MOESI_CMP_directory-L2cache.sm
3 files changed, 58 insertions(+), 24 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/ruby/MOESI_CMP_directory.py
b/configs/ruby/MOESI_CMP_directory.py
index e3385fa..18e9ef6 100644
--- a/configs/ruby/MOESI_CMP_directory.py
+++ b/configs/ruby/MOESI_CMP_directory.py
@@ -49,8 +49,13 @@
#
# Declare caches used by the protocol
#
-class L1Cache(RubyCache): pass
-class L2Cache(RubyCache): pass
+class L1Cache(RubyCache):
+ dataAccessLatency = 1
+ tagAccessLatency = 1
+
+class L2Cache(RubyCache):
+ dataAccessLatency = 20
+ tagAccessLatency = 20
def define_options(parser):
return
diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
index 9bba739..7503fb3 100644
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
@@ -42,7 +42,8 @@
: Sequencer * sequencer;
CacheMemory * L1Icache;
CacheMemory * L1Dcache;
- Cycles request_latency := 2;
+ Cycles request_latency := 1;
+ Cycles response_latency := 1;
Cycles use_timeout_latency := 50;
bool send_evictions;
@@ -182,6 +183,24 @@
return State:I;
}
+ // L1 hit latency
+ Cycles mandatoryQueueLatency(RubyRequestType type) {
+ if (type == RubyRequestType:IFETCH) {
+ return L1Icache.getTagLatency();
+ } else {
+ return L1Dcache.getTagLatency();
+ }
+ }
+
+ // Latency for responses that fetch data from cache
+ Cycles cacheResponseLatency() {
+ if (L1Dcache.getTagLatency() > response_latency) {
+ return L1Dcache.getTagLatency();
+ } else {
+ return response_latency;
+ }
+ }
+
void setState(TBE tbe, Entry cache_entry, Addr addr, State state) {
assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) ==
false);
@@ -510,7 +529,7 @@
peek(requestNetwork_in, RequestMsg) {
assert(is_valid(cache_entry));
if (in_msg.RequestorMachine == MachineType:L2Cache) {
- enqueue(responseNetwork_out, ResponseMsg, request_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) {
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.Sender := machineID;
@@ -526,7 +545,7 @@
DPRINTF(RubySlicc, "Sending data to L2: %#x\n", in_msg.addr);
}
else {
- enqueue(responseNetwork_out, ResponseMsg, request_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) {
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.Sender := machineID;
@@ -544,7 +563,7 @@
}
action(e_sendDataToL2, "ee", desc="Send data from cache to requestor") {
- enqueue(responseNetwork_out, ResponseMsg, request_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) {
assert(is_valid(cache_entry));
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA;
@@ -563,7 +582,7 @@
peek(requestNetwork_in, RequestMsg) {
assert(is_valid(cache_entry));
if (in_msg.RequestorMachine == MachineType:L2Cache) {
- enqueue(responseNetwork_out, ResponseMsg, request_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) {
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
out_msg.Sender := machineID;
@@ -578,7 +597,7 @@
DPRINTF(RubySlicc, "Sending exclusive data to L2\n");
}
else {
- enqueue(responseNetwork_out, ResponseMsg, request_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) {
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
out_msg.Sender := machineID;
@@ -597,7 +616,7 @@
action(f_sendAck, "f", desc="Send ack from cache to requestor") {
peek(requestNetwork_in, RequestMsg) {
if (in_msg.RequestorMachine == MachineType:L1Cache) {
- enqueue(responseNetwork_out, ResponseMsg, request_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, response_latency) {
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:ACK;
out_msg.Sender := machineID;
@@ -608,7 +627,7 @@
}
}
else {
- enqueue(responseNetwork_out, ResponseMsg, request_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, response_latency) {
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:ACK;
out_msg.Sender := machineID;
@@ -623,7 +642,7 @@
}
action(g_sendUnblock, "g", desc="Send unblock to memory") {
- enqueue(responseNetwork_out, ResponseMsg, request_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, response_latency) {
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:UNBLOCK;
out_msg.Sender := machineID;
@@ -635,7 +654,7 @@
}
action(gg_sendUnblockExclusive, "\g", desc="Send unblock exclusive to
memory") {
- enqueue(responseNetwork_out, ResponseMsg, request_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, response_latency) {
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE;
out_msg.Sender := machineID;
@@ -746,7 +765,7 @@
action(ub_dmaUnblockL2Cache, "ub", desc="Send dma ack to l2 cache") {
peek(requestNetwork_in, RequestMsg) {
- enqueue(responseNetwork_out, ResponseMsg, request_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, response_latency) {
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DMA_ACK;
out_msg.Sender := machineID;
@@ -765,7 +784,7 @@
assert(is_valid(tbe));
if (in_msg.RequestorMachine == MachineType:L1Cache ||
in_msg.RequestorMachine == MachineType:DMA) {
- enqueue(responseNetwork_out, ResponseMsg, request_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, response_latency) {
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.Sender := machineID;
@@ -779,7 +798,7 @@
}
}
else {
- enqueue(responseNetwork_out, ResponseMsg, request_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, response_latency) {
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.Sender := machineID;
@@ -800,7 +819,7 @@
peek(requestNetwork_in, RequestMsg) {
assert(is_valid(tbe));
if (in_msg.RequestorMachine == MachineType:L1Cache) {
- enqueue(responseNetwork_out, ResponseMsg, request_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, response_latency) {
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
out_msg.Sender := machineID;
@@ -813,7 +832,7 @@
}
}
else {
- enqueue(responseNetwork_out, ResponseMsg, request_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, response_latency) {
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
out_msg.Sender := machineID;
diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
index 53b5a94..7883a96 100644
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
@@ -40,8 +40,8 @@
machine(MachineType:L2Cache, "Token protocol")
: CacheMemory * L2cache;
- Cycles response_latency := 2;
- Cycles request_latency := 2;
+ Cycles response_latency := 1;
+ Cycles request_latency := 1;
// L2 BANK QUEUES
// From local bank of L2 cache TO the network
@@ -248,6 +248,16 @@
MachineID mapAddressToMachine(Addr addr, MachineType mtype);
void wakeUpAllBuffers(Addr a);
+ // Latency for responses that fetch data from cache
+ Cycles cacheResponseLatency() {
+ if (L2cache.getTagLatency() > response_latency) {
+ return L2cache.getTagLatency();
+ }
+ else {
+ return response_latency;
+ }
+ }
+
Entry getCacheEntry(Addr address), return_by_pointer="yes" {
return static_cast(Entry, "pointer", L2cache[address]);
}
@@ -921,7 +931,7 @@
action(d_sendDataToL1GETS, "d", desc="Send data directly to L1
requestor") {
assert(is_valid(cache_entry));
peek(L1requestNetwork_in, RequestMsg) {
- enqueue(responseNetwork_out, ResponseMsg, response_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) {
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.Sender := machineID;
@@ -941,7 +951,7 @@
action(d_sendDataToL1GETX, "\d", desc="Send data and a token from TBE to
L1 requestor") {
assert(is_valid(cache_entry));
peek(L1requestNetwork_in, RequestMsg) {
- enqueue(responseNetwork_out, ResponseMsg, response_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) {
assert(is_valid(tbe));
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
@@ -961,7 +971,7 @@
action(dd_sendDataToFwdGETX, "dd", desc="send data") {
assert(is_valid(cache_entry));
peek(requestNetwork_in, RequestMsg) {
- enqueue(responseNetwork_out, ResponseMsg, response_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) {
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
out_msg.Sender := machineID;
@@ -981,7 +991,7 @@
action(dd_sendDataToFwdGETS, "\dd", desc="send data") {
assert(is_valid(cache_entry));
peek(requestNetwork_in, RequestMsg) {
- enqueue(responseNetwork_out, ResponseMsg, response_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) {
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA;
out_msg.Sender := machineID;
@@ -1001,7 +1011,7 @@
action(dd_sendExclusiveDataToFwdGETS, "\d\d", desc="send data") {
assert(is_valid(cache_entry));
peek(requestNetwork_in, RequestMsg) {
- enqueue(responseNetwork_out, ResponseMsg, response_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) {
out_msg.addr := address;
out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
out_msg.Sender := machineID;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18414
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I72bb8dd29ee0b02da06e1addf13b266fe4d1e979
Gerrit-Change-Number: 18414
Gerrit-PatchSet: 3
Gerrit-Owner: Tiago Mück <tiago.m...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: John Alsop <johnathan.al...@amd.com>
Gerrit-Reviewer: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
Gerrit-Reviewer: Tiago Mück <tiago.m...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-CC: Xianwei Zhang <xianwei.zh...@amd.com>
Gerrit-MessageType: merged
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