Tiago Mück has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/27134 )

Change subject: cpu-o3: fix store-release issuing
......................................................................

cpu-o3: fix store-release issuing

Requests from stores with release semantics are only issued when they
are at the head of the store queue.

Change-Id: I19fbceb5ee057d3aa70175cbeec6b9b466334e8c
Signed-off-by: Tiago Mück <tiago.m...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27134
Reviewed-by: Anthony Gutierrez <anthony.gutier...@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutier...@amd.com>
Tested-by: kokoro <noreply+kok...@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938...@cloudbuild.gserviceaccount.com>
---
M src/cpu/o3/lsq_unit_impl.hh
1 file changed, 16 insertions(+), 1 deletion(-)

Approvals:
  Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass
  Gem5 Cloud Project GCB service account: Regressions pass



diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index f7fb3fe..7383c6f 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -1,6 +1,6 @@

 /*
- * Copyright (c) 2010-2014, 2017-2019 ARM Limited
+ * Copyright (c) 2010-2014, 2017-2020 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -753,6 +753,21 @@

         DynInstPtr inst = storeWBIt->instruction();
         LSQRequest* req = storeWBIt->request();
+
+        // Process store conditionals or store release after all previous
+        // stores are completed
+        if ((req->mainRequest()->isLLSC() ||
+             req->mainRequest()->isRelease()) &&
+             (storeWBIt.idx() != storeQueue.head())) {
+            DPRINTF(LSQUnit, "Store idx:%i PC:%s to Addr:%#x "
+                "[sn:%lli] is %s%s and not head of the queue\n",
+                storeWBIt.idx(), inst->pcState(),
+                req->request()->getPaddr(), inst->seqNum,
+                req->mainRequest()->isLLSC() ? "SC" : "",
+                req->mainRequest()->isRelease() ? "/Release" : "");
+            break;
+        }
+
         storeWBIt->committed() = true;

         assert(!inst->memData);

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I19fbceb5ee057d3aa70175cbeec6b9b466334e8c
Gerrit-Change-Number: 27134
Gerrit-PatchSet: 7
Gerrit-Owner: Tiago Mück <tiago.m...@arm.com>
Gerrit-Reviewer: Anthony Gutierrez <anthony.gutier...@amd.com>
Gerrit-Reviewer: Gem5 Cloud Project GCB service account <345032938...@cloudbuild.gserviceaccount.com>
Gerrit-Reviewer: Tiago Mück <tiago.m...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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