diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -6,7 +6,7 @@ from m5.objects import *
 # ====================
 
 class L1(BaseCache):
-    latency = '1ns'
+    latency = '4ns'
     block_size = 64
     mshrs = 12
     tgts_per_mshr = 8
@@ -17,7 +17,7 @@ class L1(BaseCache):
 
 class L2(BaseCache):
     block_size = 64
-    latency = '10ns'
+    latency = '14ns'
     mshrs = 92
     tgts_per_mshr = 16
     write_buffers = 8
@@ -29,11 +29,11 @@ cpus = [ MemTest() for i in xrange(nb_co
 # system simulated
 system = System(cpu = cpus, funcmem = PhysicalMemory(),
                 physmem = PhysicalMemory(),
-                membus = Bus(clock="500GHz", width=16))
+                membus = Bus(clock="500MHz", width=16))
 
 # l2cache & bus
-system.toL2Bus = Bus(clock="500GHz", width=16)
-system.l2c = L2(size='64kB', assoc=8)
+system.toL2Bus = Bus(clock="1GHz", width=16)
+system.l2c = L2(size='4MB', assoc=16)
 system.l2c.cpu_side = system.toL2Bus.port
 
 # connect l2c to membus
diff --git a/tests/quick/50.memtest/test.py b/tests/quick/50.memtest/test.py
--- a/tests/quick/50.memtest/test.py
+++ b/tests/quick/50.memtest/test.py
@@ -1,2 +1,2 @@ MemTest.max_loads=1e5
-MemTest.max_loads=1e5
-MemTest.progress_interval=1e4
+MemTest.max_loads=1e8
+MemTest.progress_interval=1e3