That all seems right, but for now since you only have 1 processor, I
would do whatever makes the kernel think that it's just two 8259As
together. I'm certain that the Linux kernel still supports that
configuration. You just need to find where the detection is done and
make sure to return the right things to make it look like that. Then
once you get further and have a better idea of what kind of APIC you
want to deal with and how multiprocessors are going to work you can
create something fancier.
Ali
On Mar 14, 2008, at 12:07 AM, Gabe Black wrote:
Ok. When the time comes I'll use PioDevice. The IO controller -
used- to be two 8259As daisy chained together, but now it's emulated
as part of a more complicated system. I think when things first boot
it looks like there's two 8259As for compatibility, but then you can
switch through different modes (sound familiar?) like virtual wire
mode and one other one who's name I forget. The one that's probably
the most relevant is the one I can't remember the name of where the
IO APIC and the local APICs (which don't exist in the 8259A model, I
don't think) communicate over the system bus to allow multiprocessor
systems and IPIs. There even used to be a special three wire APIC
bus for the APICs to communicate with each other. Even on top of
that, you can pick different routing modes to select how the
destination of IPIs should be interpretted to allow communication
between a two tiered hierarchy of clusters. It gets pretty crazy.
I'm hoping most of that doesn't get used by main stream linux just
to get it booted, although at least the IPIs would if I had built
this kernel with SMP support.
Gabe
Ali Saidi wrote:
The BasicPioDevice device only allows listening on one range, but
like the name suggests it's a the simplest kind. PioDevice has no
such restrictions you just need to do a little more work to get
things going that BasicPioDevice does for you.
Also, I believe that the two interrupt controllers are next to
each other. Anyway, it's simplest form it's a 8259A interrupt
controller:
http://www.nondot.org/sabre/os/files/MiscHW/8259A_PIC_Datasheet.pdf
http://en.wikipedia.org/wiki/Intel_8259
Ali
On Mar 13, 2008, at 11:16 PM, Gabe Black wrote:
I'm still trying to find complete information about the IO APIC,
but I believe it two IO port ranges (at least) along with some
memory locations all for the same device. The IO ports are to
mimic a simpler interrupt controller which would be formed from
two simpler cascaded devices. I don't think the way PIO devices
are set up currently will allow listening on more than one range
of addresses since they have a start and size parameter and that's
it. This isn't a critical issue now since I'm just putting IsaFake
devices in there now as placeholders, but at some point the IO
APIC will have to exist and it will have to listen to more than
one address range.
Gabe
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
