For now, I'd say just stick with the bus and get the functionality working. Only when you actually need the GART/IOMMU should you actually start worrying about it. (Which won't be for a long time.)
Nate On Fri, Mar 14, 2008 at 9:50 PM, Gabe Black <[EMAIL PROTECTED]> wrote: > I'm thinking about how to put all these bits of the x86 system > together into northbridges and southbridges and all that, and it occurs > to me that it would be nice to have a generic "link" memory object that > just connect two ports together with some bandwidth and latency. I think > we talked about that with connecting caches directly together, but I was > thinking more like if you wanted to support hypertransport and have > northbridges connected in a point to point network. What I'm envisioning > is the northbridge would have a port for the CPU, and then a port for > everything else. You'd connect links or busses or whatever you want to > the northbridge at that port to get PCIe busses and hypertransport > links. This actually sounds a lot like routers in a mesh network. I > think in x86 the northbridge isn't much more than a GART/IOMMU, a router > for hypertransport, a memory controller, and a PCIe bus controller. Most > of that could just be a router with a little bit more brains than usual > for the GART/IOMMU. Any thoughts? > > Gabe > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
