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A new Flyspray task has been opened. Details are below.
User who did this: - Clint Smullen (cws3k)
Attached to Project - M5 Bugs
Summary - SCons compatibility problems
Task Type - Bug
Category - Global/Other
Status - Unconfirmed
Assigned To -
Operating System - All
Severity - Medium
Priority - Normal
Reported Version - 2.0beta3
Due in Version -
Due Date - Undecided
Details - For both 2.0b4, and 2.0b5, M5 will not build correctly using
SCons 0.98 on either x86_64 Linux or Mac OS X 10.5.2 running on
x86_64. I had similar problems with 0.97.0d20071212 and 0.96.96 on the
Mac machine.
Example error from the Linux attempt using 0.98 is shown below:
scons: Reading SConscript files ...
Checking for C header file Python.h... yes
Checking for C library python2.4... yes
Checking for accept(0,0,0) in C++ library None... yes
Checking for zlibVersion() in C++ library z... yes
Checking for C header file fenv.h... yes
Reading /net/uf21/cws3k/m5-2.0b5/src/arch/mips/SConsopts
Reading /net/uf21/cws3k/m5-2.0b5/src/arch/alpha/SConsopts
Reading /net/uf21/cws3k/m5-2.0b5/src/arch/sparc/SConsopts
Reading /net/uf21/cws3k/m5-2.0b5/src/cpu/o3/SConsopts
Reading /net/uf21/cws3k/m5-2.0b5/src/cpu/simple/SConsopts
Building in /net/uf21/cws3k/m5-2.0b5/build/ALPHA_SE
scons: warning: The env.Copy() method is deprecated; use the
env.Clone() method instead.
File "/net/uf21/cws3k/m5-2.0b5/SConstruct", line 703, in ?
Options file /net/uf21/cws3k/m5-2.0b5/build/options/ALPHA_SE not
found,
using defaults in build_opts/ALPHA_SE
scons: done reading SConscript files.
scons: Building targets ...
createSimObjectParam(["build/ALPHA_SE/params/Bridge.hh"],
["'Bridge'"])
traceFlagsHH(["build/ALPHA_SE/base/traceflags.hh"], ["('Bus', (),
'')", "('BusAddrRanges', (), '')", "('BusBridge', (), '')", "('LLSC',
(), '')", "('MMU', (), '')", "('MemoryAccess', (), '')", "('Cache',
(), '')", "('CachePort', (), '')", "('CacheRepl', (), '')",
"('HWPrefetch', (), '')", "('IIC', (), '')", "('IICMore', (), '')",
"('Split', (), '')", "('Config', (), '')", "('Event', (), '')",
"('Fault', (), '')", "('Flow', (), '')", "('IPI', (), '')", "('IPR',
(), '')", "('Interrupt', (), '')", "('Loader', (), '')", "('Stack',
(), '')", "('SyscallVerbose', (), '')", "('TLB', (), '')", "('Thread',
(), '')", "('Timer', (), '')", "('VtoPhys', (), '')", "('Activity',
(), '')", "('Commit', (), '')", "('Context', (), '')", "('Decode', (),
'')", "('DynInst', (), '')", "('ExecEnable', (), '')", "('ExecCPSeq',
(), '')", "('ExecEffAddr', (), '')", "('ExecFetchSeq', (), '')",
"('ExecOpClass', (), '')", "('ExecRegDelta', (), '')", "('ExecResult',
(), '')", "('ExecSpeculative', (), '')", "('ExecSymbol', (), '')",
"('ExecThread', (), '')", "('ExecTicks', (), '')", "('Fetch', (),
'')", "('IntrControl', (), '')", "('PCEvent', (), '')", "('Quiesce',
(), '')", "('Exec', ('ExecEnable', 'ExecTicks', 'ExecOpClass',
'ExecThread', 'ExecEffAddr', 'ExecResult', 'ExecSymbol'), '')",
"('CommitRate', (), '')", "('IEW', (), '')", "('IQ', (), '')",
"('FreeList', (), '')", "('LSQ', (), '')", "('LSQUnit', (), '')",
"('MemDepUnit', (), '')", "('O3CPU', (), '')", "('ROB', (), '')",
"('Rename', (), '')", "('Scoreboard', (), '')", "('StoreSet', (),
'')", "('Writeback', (), '')", "('O3CPUAll', ('Fetch', 'Decode',
'Rename', 'IEW', 'Commit', 'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit',
'StoreSet', 'MemDepUnit', 'DynInst', 'O3CPU', 'Activity',
'Scoreboard', 'Writeback'), '')", "('MemTest', (), '')",
"('SimpleCPU', (), '')", "('Annotate', (), '')", "('GDBAcc', (), '')",
"('GDBExtra', (), '')", "('GDBMisc', (), '')", "('GDBRead', (), '')",
"('GDBRecv', (), '')", "('GDBSend', (), '')", "('GDBWrite', (), '')",
"('SQL', (), '')", "('StatEvents', (), '')", "('GDBAll', ('GDBMisc',
'GDBAcc', 'GDBRead', 'GDBWrite', 'GDBSend', 'GDBRecv', 'GDBExtra'),
'')"])
createSimObjectParam(["build/ALPHA_SE/params/MemObject.hh"],
["'MemObject'"])
createSimObjectParam(["build/ALPHA_SE/params/SimObject.hh"],
["'SimObject'"])
Defining NO_FAST_ALLOC as 0 in build/ALPHA_SE/config/no_fast_alloc.hh.
Generating switch header build/ALPHA_SE/arch/isa_traits.hh
/usr/bin/python build/ALPHA_SE/arch/isa_parser.py
build/ALPHA_SE/cpu/cpu_models.py
build/ALPHA_SE/arch/alpha/isa/main.isa build/ALPHA_SE/arch/alpha
AtomicSimpleCPU O3CPU TimingSimpleCPU
yacc: Generating LALR parsing table...
Generating build/ALPHA_SE/arch/alpha/decoder.hh
Generating build/ALPHA_SE/arch/alpha/decoder.cc
Generating build/ALPHA_SE/arch/alpha/atomic_simple_cpu_exec.cc
Generating build/ALPHA_SE/arch/alpha/o3_cpu_exec.cc
Generating build/ALPHA_SE/arch/alpha/timing_simple_cpu_exec.cc
Generating build/ALPHA_SE/arch/alpha/max_inst_regs.hh
Defining FULL_SYSTEM as 0 in build/ALPHA_SE/config/full_system.hh.
g++ -o build/ALPHA_SE/mem/bridge.do -c -pipe -fno-strict-aliasing
-Wall -Wno-sign-compare -Werror -Wundef -ggdb3 -DTHE_ISA=ALPHA_ISA
-DDEBUG -DTRACING_ON=1 -Iext/dnet -I/usr/include/python2.4
-Ibuild/libelf -Ibuild/ALPHA_SE build/ALPHA_SE/mem/bridge.cc
createSimObjectParam(["build/ALPHA_SE/params/Bus.hh"], ["'Bus'"])
g++ -o build/ALPHA_SE/mem/bus.do -c -pipe -fno-strict-aliasing -Wall
-Wno-sign-compare -Werror -Wundef -ggdb3 -DTHE_ISA=ALPHA_ISA -DDEBUG
-DTRACING_ON=1 -Iext/dnet -I/usr/include/python2.4 -Ibuild/libelf
-Ibuild/ALPHA_SE build/ALPHA_SE/mem/bus.cc
createSimObjectParam(["build/ALPHA_SE/params/DRAMMemory.hh"],
["'DRAMMemory'"])
createSimObjectParam(["build/ALPHA_SE/params/PhysicalMemory.hh"],
["'PhysicalMemory'"])
g++ -o build/ALPHA_SE/mem/dram.do -c -pipe -fno-strict-aliasing -Wall
-Wno-sign-compare -Werror -Wundef -ggdb3 -DTHE_ISA=ALPHA_ISA -DDEBUG
-DTRACING_ON=1 -Iext/dnet -I/usr/include/python2.4 -Ibuild/libelf
-Ibuild/ALPHA_SE build/ALPHA_SE/mem/dram.cc
g++ -o build/ALPHA_SE/mem/mem_object.do -c -pipe -fno-strict-aliasing
-Wall -Wno-sign-compare -Werror -Wundef -ggdb3 -DTHE_ISA=ALPHA_ISA
-DDEBUG -DTRACING_ON=1 -Iext/dnet -I/usr/include/python2.4
-Ibuild/libelf -Ibuild/ALPHA_SE build/ALPHA_SE/mem/mem_object.cc
g++ -o build/ALPHA_SE/mem/packet.do -c -pipe -fno-strict-aliasing
-Wall -Wno-sign-compare -Werror -Wundef -ggdb3 -DTHE_ISA=ALPHA_ISA
-DDEBUG -DTRACING_ON=1 -Iext/dnet -I/usr/include/python2.4
-Ibuild/libelf -Ibuild/ALPHA_SE build/ALPHA_SE/mem/packet.cc
g++ -o build/ALPHA_SE/mem/physical.do -c -pipe -fno-strict-aliasing
-Wall -Wno-sign-compare -Werror -Wundef -ggdb3 -DTHE_ISA=ALPHA_ISA
-DDEBUG -DTRACING_ON=1 -Iext/dnet -I/usr/include/python2.4
-Ibuild/libelf -Ibuild/ALPHA_SE build/ALPHA_SE/mem/physical.cc
g++ -o build/ALPHA_SE/mem/port.do -c -pipe -fno-strict-aliasing -Wall
-Wno-sign-compare -Werror -Wundef -ggdb3 -DTHE_ISA=ALPHA_ISA -DDEBUG
-DTRACING_ON=1 -Iext/dnet -I/usr/include/python2.4 -Ibuild/libelf
-Ibuild/ALPHA_SE build/ALPHA_SE/mem/port.cc
g++ -o build/ALPHA_SE/mem/tport.do -c -pipe -fno-strict-aliasing -Wall
-Wno-sign-compare -Werror -Wundef -ggdb3 -DTHE_ISA=ALPHA_ISA -DDEBUG
-DTRACING_ON=1 -Iext/dnet -I/usr/include/python2.4 -Ibuild/libelf
-Ibuild/ALPHA_SE build/ALPHA_SE/mem/tport.cc
Generating switch header build/ALPHA_SE/arch/faults.hh
Generating switch header build/ALPHA_SE/arch/tlb.hh
createEnumParam(["build/ALPHA_SE/enums/MemoryMode.hh"],
["'MemoryMode'"])
createSimObjectParam(["build/ALPHA_SE/params/System.hh"],
["'System'"])
Generating switch header build/ALPHA_SE/arch/vtophys.hh
createSimObjectParam(["build/ALPHA_SE/params/AlphaDTB.hh"],
["'AlphaDTB'"])
createSimObjectParam(["build/ALPHA_SE/params/AlphaITB.hh"],
["'AlphaITB'"])
Defining ALPHA_TLASER as 0 in build/ALPHA_SE/config/alpha_tlaser.hh.
Generating switch header build/ALPHA_SE/arch/regfile.hh
Generating switch header build/ALPHA_SE/arch/types.hh
createSimObjectParam(["build/ALPHA_SE/params/AlphaTLB.hh"],
["'AlphaTLB'"])
g++ -o build/ALPHA_SE/mem/page_table.do -c -pipe -fno-strict-aliasing
-Wall -Wno-sign-compare -Werror -Wundef -ggdb3 -DTHE_ISA=ALPHA_ISA
-DDEBUG -DTRACING_ON=1 -Iext/dnet -I/usr/include/python2.4
-Ibuild/libelf -Ibuild/ALPHA_SE build/ALPHA_SE/mem/page_table.cc
g++ -o build/ALPHA_SE/mem/translating_port.do -c -pipe
-fno-strict-aliasing -Wall -Wno-sign-compare -Werror -Wundef -ggdb3
-DTHE_ISA=ALPHA_ISA -DDEBUG -DTRACING_ON=1 -Iext/dnet
-I/usr/include/python2.4 -Ibuild/libelf -Ibuild/ALPHA_SE
build/ALPHA_SE/mem/translating_port.cc
Generating switch header build/ALPHA_SE/arch/interrupts.hh
createSimObjectParam(["build/ALPHA_SE/params/BaseCache.hh"],
["'BaseCache'"])
Generating switch header build/ALPHA_SE/arch/utility.hh
Generating static_inst_exec_sigs.hh: AtomicSimpleCPU, O3CPU,
TimingSimpleCPU
createEnumParam(["build/ALPHA_SE/enums/OpClass.hh"], ["'OpClass'"])
createEnumParam(["build/ALPHA_SE/enums/Prefetch.hh"], ["'Prefetch'"])
g++ -o build/ALPHA_SE/mem/cache/base.do -c -pipe -fno-strict-aliasing
-Wall -Wno-sign-compare -Werror -Wundef -ggdb3 -DTHE_ISA=ALPHA_ISA
-DDEBUG -DTRACING_ON=1 -Iext/dnet -I/usr/include/python2.4
-Ibuild/libelf -Ibuild/ALPHA_SE build/ALPHA_SE/mem/cache/base.cc
g++ -o build/ALPHA_SE/mem/cache/cache.do -c -pipe -fno-strict-aliasing
-Wall -Wno-sign-compare -Werror -Wundef -ggdb3 -DTHE_ISA=ALPHA_ISA
-DDEBUG -DTRACING_ON=1 -Iext/dnet -I/usr/include/python2.4
-Ibuild/libelf -Ibuild/ALPHA_SE build/ALPHA_SE/mem/cache/cache.cc
build/ALPHA_SE/mem/cache/cache.cc:39:31: error: mem/config/cache.hh:
No such file or directory
scons: *** [build/ALPHA_SE/mem/cache/cache.do] Error 1
scons: building terminated because of errors.
More information can be found at the following URL:
http://www.m5sim.org/flyspray/task/308
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