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FS#302 - Bring up distinction between trap and faulting instruction. User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - Bring up distinction between trap and faulting instruction. Task Type - Minor Enhancement Category - ISA Support Status - New Assigned To - Gabe Black Operating System - All Severity - Low Priority - Normal Reported Version - 2.0beta3 Due in Version - 2.1 Due Date - Undecided Percent Complete - 0% Details - There is a distinction between an instruction which unexpectedly faults, like a load, and an instruction that traps on purpose like a tcc in SPARC. An instruction which faults and is not retried should be counted as completed and traced, while instructions which just fault should not. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/302 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
