[m5-dev] local APIC timer and bus frequency

[Gabe Black]

   The kernel is now getting to a point where it's trying to calibrate 
the timer in the local APIC against the TSC register. In order to mimic 
that, I'm going to need to create an event to fire when the timer is 
supposed to go off. This is enough of an impetus to separate the local 
APIC into it's own device on the bus just outside of the CPU. That means 
I need to solve some issues I've been putting off, namely making sure 
there's exactly one local APIC per cpu and that they know about each 
other. One topology is that the local APIC acts as an intermediary 
between the CPU and the interconnect, and the other is with the APIC as 
a peer. The latter won't work so well with non-bus interconnects I don't 
think. Also, each APIC has to know what CPU it's associated with so it 
can return the right ID number and to have a pointer to make it 
interrupt. Also, the APIC needs to know what the frequency is of the 
interconnect it's connected to since it runs it's timer off of a divided 
version of that clock. What do people think?

Gabe
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