changeset 90d6811d5ea6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=90d6811d5ea6
description:
m5ops: clean up the m5ops stuff.
- insert warnings for deprecated m5ops
- reserve opcodes for Ali's stuff
- remove code for stuff that has been deprecated forever
- simplify m5op_alpha
diffstat:
4 files changed, 5 insertions(+), 27 deletions(-)
src/arch/alpha/isa/decoder.isa | 4 ++--
src/sim/pseudo_inst.cc | 3 ---
util/m5/m5op_alpha.S | 3 +++
util/m5/m5ops.h | 22 ----------------------
diffs (truncated from 332 to 300 lines):
diff -r 288b54c2fd8d -r 90d6811d5ea6 src/arch/alpha/isa/decoder.isa
--- a/src/arch/alpha/isa/decoder.isa Fri Jul 11 08:52:50 2008 -0700
+++ b/src/arch/alpha/isa/decoder.isa Fri Jul 11 08:52:50 2008 -0700
@@ -806,14 +806,15 @@
0x04: quiesceTime({{
R0 = PseudoInst::quiesceTime(xc->tcBase());
}}, IsNonSpeculative, IsUnverifiable);
- 0x10: ivlb({{
- warn_once("Obsolete M5 instruction ivlb encountered.\n");
+ 0x10: deprecated_ivlb({{
+ warn_once("Obsolete M5 ivlb instruction encountered.\n");
}});
- 0x11: ivle({{
- warn_once("Obsolete M5 instruction ivlb encountered.\n");
+ 0x11: deprecated_ivle({{
+ warn_once("Obsolete M5 ivlb instruction encountered.\n");
}});
- 0x20: m5exit_old({{
- PseudoInst::m5exit_old(xc->tcBase());
+ 0x20: deprecated_exit ({{
+ warn_once("deprecated M5 exit instruction encountered.\n");
+ PseudoInst::m5exit(xc->tcBase(), 0);
}}, No_OpClass, IsNonSpeculative);
0x21: m5exit({{
PseudoInst::m5exit(xc->tcBase(), R16);
@@ -821,7 +822,9 @@
0x31: loadsymbol({{
PseudoInst::loadsymbol(xc->tcBase());
}}, No_OpClass, IsNonSpeculative);
- 0x30: initparam({{ Ra =
xc->tcBase()->getCpuPtr()->system->init_param; }});
+ 0x30: initparam({{
+ Ra = xc->tcBase()->getCpuPtr()->system->init_param;
+ }});
0x40: resetstats({{
PseudoInst::resetstats(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
@@ -849,11 +852,20 @@
0x54: m5panic({{
panic("M5 panic instruction called at pc=%#x.", xc->readPC());
}}, IsNonSpeculative);
- 0x55: m5anBegin({{
- PseudoInst::anBegin(xc->tcBase(), R16);
+ 0x55: m5reserved1({{
+ warn("M5 reserved opcode ignored");
}}, IsNonSpeculative);
- 0x56: m5anWait({{
- PseudoInst::anWait(xc->tcBase(), R16, R17);
+ 0x56: m5reserved2({{
+ warn("M5 reserved opcode ignored");
+ }}, IsNonSpeculative);
+ 0x57: m5reserved3({{
+ warn("M5 reserved opcode ignored");
+ }}, IsNonSpeculative);
+ 0x58: m5reserved4({{
+ warn("M5 reserved opcode ignored");
+ }}, IsNonSpeculative);
+ 0x59: m5reserved5({{
+ warn("M5 reserved opcode ignored");
}}, IsNonSpeculative);
}
}
diff -r 288b54c2fd8d -r 90d6811d5ea6 src/sim/pseudo_inst.cc
--- a/src/sim/pseudo_inst.cc Fri Jul 11 08:52:50 2008 -0700
+++ b/src/sim/pseudo_inst.cc Fri Jul 11 08:52:50 2008 -0700
@@ -124,12 +124,6 @@
}
void
-m5exit_old(ThreadContext *tc)
-{
- exitSimLoop("m5_exit_old instruction encountered");
-}
-
-void
m5exit(ThreadContext *tc, Tick delay)
{
Tick when = curTick + delay * Clock::Int::ns;
@@ -221,21 +215,6 @@
tc->getSystemPtr()->kernelSymtab->insert(addr,symbol);
}
-
-void
-anBegin(ThreadContext *tc, uint64_t cur)
-{
- Annotate::annotations.add(tc->getSystemPtr(), 0, cur >> 32, cur &
- 0xFFFFFFFF, 0,0);
-}
-
-void
-anWait(ThreadContext *tc, uint64_t cur, uint64_t wait)
-{
- Annotate::annotations.add(tc->getSystemPtr(), 0, cur >> 32, cur &
- 0xFFFFFFFF, wait >> 32, wait & 0xFFFFFFFF);
-}
-
void
dumpresetstats(ThreadContext *tc, Tick delay, Tick period)
diff -r 288b54c2fd8d -r 90d6811d5ea6 src/sim/pseudo_inst.hh
--- a/src/sim/pseudo_inst.hh Fri Jul 11 08:52:50 2008 -0700
+++ b/src/sim/pseudo_inst.hh Fri Jul 11 08:52:50 2008 -0700
@@ -48,7 +48,6 @@
void quiesceCycles(ThreadContext *tc, uint64_t cycles);
uint64_t quiesceTime(ThreadContext *tc);
void m5exit(ThreadContext *tc, Tick delay);
-void m5exit_old(ThreadContext *tc);
void loadsymbol(ThreadContext *xc);
void resetstats(ThreadContext *tc, Tick delay, Tick period);
void dumpstats(ThreadContext *tc, Tick delay, Tick period);
@@ -59,7 +58,5 @@
void debugbreak(ThreadContext *tc);
void switchcpu(ThreadContext *tc);
void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr);
-void anBegin(ThreadContext *tc, uint64_t cur);
-void anWait(ThreadContext *tc, uint64_t cur, uint64_t wait);
/* namespace PsuedoInst */ }
diff -r 288b54c2fd8d -r 90d6811d5ea6 util/m5/m5op_alpha.S
--- a/util/m5/m5op_alpha.S Fri Jul 11 08:52:50 2008 -0700
+++ b/util/m5/m5op_alpha.S Fri Jul 11 08:52:50 2008 -0700
@@ -48,6 +48,12 @@
#define END(func) \
.end func
+#define SIMPLE_OP(_f, _o) \
+ LEAF(_f) \
+ _o; \
+ RET; \
+ END(_f)
+
#define ARM(reg) INST(m5_op, reg, 0, arm_func)
#define QUIESCE INST(m5_op, 0, 0, quiesce_func)
#define QUIESCENS(r1) INST(m5_op, r1, 0, quiescens_func)
@@ -65,125 +71,24 @@
#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func)
#define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, addsymbol_func)
#define PANIC INST(m5_op, 0, 0, panic_func)
-#define AN_BEGIN(r1) INST(m5_op, r1, 0, anbegin_func)
-#define AN_WAIT(r1,r2) INST(m5_op, r1, r2, anwait_func)
.set noreorder
- .align 4
-LEAF(arm)
- ARM(16)
- RET
-END(arm)
+SIMPLE_OP(arm, ARM(16))
+SIMPLE_OP(quiesce, QUIESCE)
+SIMPLE_OP(quiesceNs, QUIESCENS(16))
+SIMPLE_OP(quiesceCycle, QUIESCECYC(16))
+SIMPLE_OP(quiesceTime, QUIESCETIME)
+SIMPLE_OP(m5_exit, M5EXIT(16))
+SIMPLE_OP(m5_initparam, INITPARAM(0))
+SIMPLE_OP(m5_loadsymbol, LOADSYMBOL(0))
+SIMPLE_OP(m5_reset_stats, RESET_STATS(16, 17))
+SIMPLE_OP(m5_dump_stats, DUMP_STATS(16, 17))
+SIMPLE_OP(m5_dumpreset_stats, DUMPRST_STATS(16, 17))
+SIMPLE_OP(m5_checkpoint, CHECKPOINT(16, 17))
+SIMPLE_OP(m5_readfile, READFILE)
+SIMPLE_OP(m5_debugbreak, DEBUGBREAK)
+SIMPLE_OP(m5_switchcpu, SWITCHCPU)
+SIMPLE_OP(m5_addsymbol, ADDSYMBOL(16, 17))
+SIMPLE_OP(m5_panic, PANIC)
- .align 4
-LEAF(quiesce)
- QUIESCE
- RET
-END(quiesce)
-
- .align 4
-LEAF(quiesceNs)
- QUIESCENS(16)
- RET
-END(quiesceNs)
-
- .align 4
-LEAF(quiesceCycle)
- QUIESCECYC(16)
- RET
-END(quiesceCycle)
-
- .align 4
-LEAF(quiesceTime)
- QUIESCETIME
- RET
-END(quiesceTime)
-
- .align 4
-LEAF(m5_exit)
- M5EXIT(16)
- RET
-END(m5_exit)
-
- .align 4
-LEAF(m5_initparam)
- INITPARAM(0)
- RET
-END(m5_initparam)
-
- .align 4
-LEAF(m5_loadsymbol)
- LOADSYMBOL(0)
- RET
-END(m5_loadsymbol)
-
- .align 4
-LEAF(m5_reset_stats)
- RESET_STATS(16, 17)
- RET
-END(m5_reset_stats)
-
- .align 4
-LEAF(m5_dump_stats)
- DUMP_STATS(16, 17)
- RET
-END(m5_dump_stats)
-
- .align 4
-LEAF(m5_dumpreset_stats)
- DUMPRST_STATS(16, 17)
- RET
-END(m5_dumpreset_stats)
-
- .align 4
-LEAF(m5_checkpoint)
- CHECKPOINT(16, 17)
- RET
-END(m5_checkpoint)
-
- .align 4
-LEAF(m5_readfile)
- READFILE
- RET
-END(m5_readfile)
-
- .align 4
-LEAF(m5_debugbreak)
- DEBUGBREAK
- RET
-END(m5_debugbreak)
-
- .align 4
-LEAF(m5_switchcpu)
- SWITCHCPU
- RET
-END(m5_switchcpu)
-
- .align 4
-LEAF(m5_addsymbol)
- ADDSYMBOL(16, 17)
- RET
-END(m5_addsymbol)
-
- .align 4
-LEAF(m5_panic)
- PANIC
- RET
-END(m5_panic)
-
-
- .align 4
-LEAF(m5_anbegin)
- AN_BEGIN(16)
- RET
-END(m5_anbegin)
-
-
- .align 4
-LEAF(m5_anwait)
- AN_WAIT(16,17)
- RET
-END(m5_anwait)
-
-
diff -r 288b54c2fd8d -r 90d6811d5ea6 util/m5/m5ops.h
--- a/util/m5/m5ops.h Fri Jul 11 08:52:50 2008 -0700
+++ b/util/m5/m5ops.h Fri Jul 11 08:52:50 2008 -0700
@@ -29,26 +29,29 @@
* Ali Saidi
*/
-#define arm_func 0x00
-#define quiesce_func 0x01
-#define quiescens_func 0x02
-#define quiescecycle_func 0x03
-#define quiescetime_func 0x04
-#define ivlb 0x10 // obsolete
-#define ivle 0x11 // obsolete
-#define exit_old_func 0x20 // deprecated!
-#define exit_func 0x21
-#define initparam_func 0x30
-#define loadsymbol_func 0x31
-#define resetstats_func 0x40
-#define dumpstats_func 0x41
-#define dumprststats_func 0x42
-#define ckpt_func 0x43
-#define readfile_func 0x50
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