changeset 17c0c17726ff in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=17c0c17726ff
description:
Changed BaseCPU::ProfileEvent's interval member to be of type Tick.
This was done to be consistent with its
python type of a latency. In addition, the multiple definitions of
profile in the different cpu models caused
problems for intialization of the interval value. If a child class's
profile value was defined, the parent
BaseCPU::ProfileEvent interval field would be initialized with a
garbage value. The fix was to remove the
multiple redifitions of profile in the child CPU classes.
diffstat:
4 files changed, 1 insertion(+), 4 deletions(-)
src/cpu/base.hh | 2 +-
src/cpu/ozone/OzoneCPU.py | 1 -
src/cpu/simple/AtomicSimpleCPU.py | 1 -
src/cpu/simple/TimingSimpleCPU.py | 1 -
diffs (91 lines):
diff -r 24d9f0941095 -r 17c0c17726ff src/cpu/CheckerCPU.py
--- a/src/cpu/CheckerCPU.py Wed Aug 13 17:41:58 2008 -0400
+++ b/src/cpu/CheckerCPU.py Mon Aug 18 10:50:58 2008 -0700
@@ -40,5 +40,3 @@
"If a load result is incorrect, only print a warning and do not exit")
function_trace = Param.Bool(False, "Enable function trace")
function_trace_start = Param.Tick(0, "Cycle to start function trace")
- if build_env['FULL_SYSTEM']:
- profile = Param.Latency('0ns', "trace the kernel stack")
diff -r 24d9f0941095 -r 17c0c17726ff src/cpu/base.cc
--- a/src/cpu/base.cc Wed Aug 13 17:41:58 2008 -0400
+++ b/src/cpu/base.cc Mon Aug 18 10:50:58 2008 -0700
@@ -357,7 +357,7 @@
#if FULL_SYSTEM
-BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, int _interval)
+BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
: Event(&mainEventQueue), cpu(_cpu), interval(_interval)
{ }
diff -r 24d9f0941095 -r 17c0c17726ff src/cpu/base.hh
--- a/src/cpu/base.hh Wed Aug 13 17:41:58 2008 -0400
+++ b/src/cpu/base.hh Mon Aug 18 10:50:58 2008 -0700
@@ -122,10 +122,10 @@
{
private:
BaseCPU *cpu;
- int interval;
+ Tick interval;
public:
- ProfileEvent(BaseCPU *cpu, int interval);
+ ProfileEvent(BaseCPU *cpu, Tick interval);
void process();
};
ProfileEvent *profileEvent;
diff -r 24d9f0941095 -r 17c0c17726ff src/cpu/o3/O3Checker.py
--- a/src/cpu/o3/O3Checker.py Wed Aug 13 17:41:58 2008 -0400
+++ b/src/cpu/o3/O3Checker.py Mon Aug 18 10:50:58 2008 -0700
@@ -39,5 +39,3 @@
"If a load result is incorrect, only print a warning and do not exit")
function_trace = Param.Bool(False, "Enable function trace")
function_trace_start = Param.Tick(0, "Cycle to start function trace")
- if build_env['FULL_SYSTEM']:
- profile = Param.Latency('0ns', "trace the kernel stack")
diff -r 24d9f0941095 -r 17c0c17726ff src/cpu/ozone/OzoneCPU.py
--- a/src/cpu/ozone/OzoneCPU.py Wed Aug 13 17:41:58 2008 -0400
+++ b/src/cpu/ozone/OzoneCPU.py Mon Aug 18 10:50:58 2008 -0700
@@ -40,8 +40,6 @@
if build_env['USE_CHECKER']:
checker = Param.BaseCPU("Checker CPU")
- if build_env['FULL_SYSTEM']:
- profile = Param.Latency('0ns', "trace the kernel stack")
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
diff -r 24d9f0941095 -r 17c0c17726ff src/cpu/ozone/OzoneChecker.py
--- a/src/cpu/ozone/OzoneChecker.py Wed Aug 13 17:41:58 2008 -0400
+++ b/src/cpu/ozone/OzoneChecker.py Mon Aug 18 10:50:58 2008 -0700
@@ -39,5 +39,3 @@
"If a load result is incorrect, only print a warning and do not exit")
function_trace = Param.Bool(False, "Enable function trace")
function_trace_start = Param.Tick(0, "Cycle to start function trace")
- if build_env['FULL_SYSTEM']:
- profile = Param.Latency('0ns', "trace the kernel stack")
diff -r 24d9f0941095 -r 17c0c17726ff src/cpu/simple/AtomicSimpleCPU.py
--- a/src/cpu/simple/AtomicSimpleCPU.py Wed Aug 13 17:41:58 2008 -0400
+++ b/src/cpu/simple/AtomicSimpleCPU.py Mon Aug 18 10:50:58 2008 -0700
@@ -37,8 +37,6 @@
simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
function_trace = Param.Bool(False, "Enable function trace")
function_trace_start = Param.Tick(0, "Cycle to start function trace")
- if build_env['FULL_SYSTEM']:
- profile = Param.Latency('0ns', "trace the kernel stack")
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
physmem_port = Port("Physical Memory Port")
diff -r 24d9f0941095 -r 17c0c17726ff src/cpu/simple/TimingSimpleCPU.py
--- a/src/cpu/simple/TimingSimpleCPU.py Wed Aug 13 17:41:58 2008 -0400
+++ b/src/cpu/simple/TimingSimpleCPU.py Mon Aug 18 10:50:58 2008 -0700
@@ -34,8 +34,6 @@
type = 'TimingSimpleCPU'
function_trace = Param.Bool(False, "Enable function trace")
function_trace_start = Param.Tick(0, "Cycle to start function trace")
- if build_env['FULL_SYSTEM']:
- profile = Param.Latency('0ns', "trace the kernel stack")
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
_mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port']
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