changeset eaeed2bdf50d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=eaeed2bdf50d
description:
CPU: Get rid of two more duplicated CPU params.
diffstat:
2 files changed, 2 deletions(-)
src/cpu/simple/AtomicSimpleCPU.py | 1 -
src/cpu/simple/TimingSimpleCPU.py | 1 -
diffs (24 lines):
diff -r 17c0c17726ff -r eaeed2bdf50d src/cpu/simple/AtomicSimpleCPU.py
--- a/src/cpu/simple/AtomicSimpleCPU.py Mon Aug 18 10:50:58 2008 -0700
+++ b/src/cpu/simple/AtomicSimpleCPU.py Tue Aug 19 21:59:09 2008 -0700
@@ -35,8 +35,6 @@
width = Param.Int(1, "CPU width")
simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
- function_trace = Param.Bool(False, "Enable function trace")
- function_trace_start = Param.Tick(0, "Cycle to start function trace")
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
physmem_port = Port("Physical Memory Port")
diff -r 17c0c17726ff -r eaeed2bdf50d src/cpu/simple/TimingSimpleCPU.py
--- a/src/cpu/simple/TimingSimpleCPU.py Mon Aug 18 10:50:58 2008 -0700
+++ b/src/cpu/simple/TimingSimpleCPU.py Tue Aug 19 21:59:09 2008 -0700
@@ -32,8 +32,6 @@
class TimingSimpleCPU(BaseSimpleCPU):
type = 'TimingSimpleCPU'
- function_trace = Param.Bool(False, "Enable function trace")
- function_trace_start = Param.Tick(0, "Cycle to start function trace")
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
_mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port']
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
