Actually, no. In the original files, tabs were replaced with enough spaces so that the things after them still started on column boundaries. When in a diff, there's a + or - at the start of the line, so one less space is needed to line up properly. Fortunately there was only one patch which didn't apply without modification, and that was easy to fix by hand.
Gabe Ali Saidi wrote: > run expand on the patch files before trying to apply them... > Everything should work fine. > > Ali > > On Sep 10, 2008, at 4:44 PM, [EMAIL PROTECTED] wrote: > > >> I really hope this isn't going to make applying all my patches >> significantly >> harder... >> >> Gabe >> >> Quoting Ali Saidi <[EMAIL PROTECTED]>: >> >> >>> changeset 3af77710f397 in /z/repo/m5 >>> details: http://repo.m5sim.org/m5?cmd=changeset;node=3af77710f397 >>> description: >>> style: Remove non-leading tabs everywhere they shouldn't be. >>> Developers >>> should configure their editors to not insert tabs >>> >>> diffstat: >>> >>> 69 files changed, 427 insertions(+), 682 deletions(-) >>> configs/common/ >>> Benchmarks.py | 17 >>> src/arch/alpha/ >>> aout_machdep.h | 21 >>> src/arch/alpha/ >>> floatregfile.hh | 1 >>> src/arch/alpha/ >>> ipr.cc | 53 >>> -- >>> src/arch/alpha/ >>> ipr.hh | 54 >>> +- >>> src/arch/alpha/ >>> isa_traits.hh | 4 >>> src/arch/alpha/linux/ >>> linux.cc | 16 >>> src/arch/alpha/linux/ >>> linux.hh | 14 >>> src/arch/alpha/ >>> miscregfile.hh | 4 >>> src/arch/alpha/ >>> osfpal.cc | 193 >>> ++----- >>> src/arch/alpha/ >>> pagetable.hh | 8 >>> src/arch/alpha/ >>> regfile.hh | 1 >>> src/arch/alpha/ >>> system.cc | 2 >>> src/arch/alpha/tru64/ >>> tru64.cc | 16 >>> src/arch/alpha/tru64/ >>> tru64.hh | 14 >>> src/arch/mips/ >>> isa_traits.hh | 4 >>> src/arch/mips/linux/ >>> linux.cc | 16 >>> src/arch/mips/linux/ >>> linux.hh | 14 >>> src/arch/mips/regfile/ >>> regfile.hh | 6 >>> src/arch/mips/ >>> system.cc | 2 >>> src/arch/mips/ >>> tlb.hh | 2 >>> src/arch/sparc/linux/ >>> linux.cc | 16 >>> src/arch/sparc/linux/ >>> linux.hh | 14 >>> src/arch/sparc/ >>> miscregfile.hh | 22 >>> src/arch/sparc/ >>> regfile.hh | 1 >>> src/arch/sparc/solaris/ >>> solaris.cc | 18 >>> src/arch/sparc/solaris/ >>> solaris.hh | 10 >>> src/arch/sparc/ >>> sparc_traits.hh | 1 >>> src/arch/x86/isa/insts/general_purpose/ >>> cache_and_memory_management.py | 4 >>> src/arch/x86/isa/insts/general_purpose/data_conversion/ >>> ascii_adjust.py | 2 >>> src/arch/x86/isa/insts/general_purpose/ >>> load_segment_registers.py | 4 >>> src/arch/x86/isa/insts/general_purpose/ >>> system_calls.py | 2 >>> src/arch/x86/linux/ >>> linux.hh | 14 >>> src/base/ >>> crc.cc | 1 >>> src/base/ >>> inifile.hh | 1 >>> src/base/loader/ >>> coff_symconst.h | 12 >>> src/base/stats/ >>> flags.hh | 9 >>> src/cpu/ >>> base_dyn_inst.hh | 1 >>> src/cpu/checker/ >>> cpu_impl.hh | 2 >>> src/cpu/memtest/ >>> memtest.hh | 2 >>> src/cpu/o3/alpha/ >>> dyn_inst.hh | 1 >>> src/cpu/o3/mips/ >>> dyn_inst.hh | 1 >>> src/cpu/ >>> simple_thread.cc | 1 >>> src/cpu/ >>> static_inst.hh | 16 >>> src/dev/alpha/ >>> access.h | 14 >>> src/dev/ >>> etherdump.cc | 8 >>> src/dev/mips/ >>> access.h | 16 >>> src/dev/ >>> ns_gige.hh | 3 >>> src/dev/ >>> pcireg.h | 11 >>> src/kern/linux/ >>> linux.hh | 28 >>> - >>> src/kern/ >>> operatingsystem.hh | 1 >>> src/kern/solaris/ >>> solaris.hh | 22 >>> src/kern/tru64/ >>> mbuf.hh | 33 >>> - >>> src/kern/tru64/ >>> tru64_syscalls.cc | 243 >>> ++++------ >>> src/mem/cache/ >>> blk.hh | 1 >>> src/mem/cache/ >>> builder.cc | 26 >>> - >>> src/mem/cache/prefetch/ >>> stride.cc | 2 >>> src/mem/ >>> physical.hh | 2 >>> src/mem/ >>> request.hh | 6 >>> src/sim/ >>> async.hh | 5 >>> src/sim/ >>> host.hh | 2 >>> src/sim/ >>> process.hh | 2 >>> src/sim/ >>> serialize.cc | 14 >>> src/sim/ >>> serialize.hh | 13 >>> src/sim/ >>> sim_events.hh | 6 >>> src/sim/ >>> syscall_emul.hh | 2 >>> util/m5/ >>> m5op_alpha.S | 5 >>> util/m5/ >>> m5ops.h | 21 >>> util/term/ >>> term.c | 6 >>> >>> diffs (truncated from 7116 to 300 lines): >>> >>> diff -r cdb571ebb4a8 -r 3af77710f397 configs/common/Benchmarks.py >>> --- a/configs/common/Benchmarks.py Tue Sep 09 16:27:17 2008 -0700 >>> +++ b/configs/common/Benchmarks.py Wed Sep 10 14:26:15 2008 -0400 >>> @@ -59,46 +59,46 @@ >>> 'PovrayBench': [SysConfig('povray-bench.rcS', '512MB', >>> 'povray.img')], >>> 'PovrayAutumn': [SysConfig('povray-autumn.rcS', '512MB', >>> 'povray.img')], >>> >>> - 'NetperfStream': [SysConfig('netperf-stream-client.rcS'), >>> + 'NetperfStream': [SysConfig('netperf-stream-client.rcS'), >>> SysConfig('netperf-server.rcS')], >>> - 'NetperfStreamUdp': [SysConfig('netperf-stream-udp-client.rcS'), >>> + 'NetperfStreamUdp': [SysConfig('netperf-stream-udp-client.rcS'), >>> SysConfig('netperf-server.rcS')], >>> - 'NetperfUdpLocal': [SysConfig('netperf-stream-udp-local.rcS')], >>> - 'NetperfStreamNT': [SysConfig('netperf-stream-nt-client.rcS'), >>> + 'NetperfUdpLocal': [SysConfig('netperf-stream-udp-local.rcS')], >>> + 'NetperfStreamNT': [SysConfig('netperf-stream-nt-client.rcS'), >>> SysConfig('netperf-server.rcS')], >>> - 'NetperfMaerts': [SysConfig('netperf-maerts-client.rcS'), >>> + 'NetperfMaerts': [SysConfig('netperf-maerts-client.rcS'), >>> SysConfig('netperf-server.rcS')], >>> - 'SurgeStandard': [SysConfig('surge-server.rcS', '512MB'), >>> + 'SurgeStandard': [SysConfig('surge-server.rcS', '512MB'), >>> SysConfig('surge-client.rcS', '256MB')], >>> - 'SurgeSpecweb': [SysConfig('spec-surge-server.rcS', '512MB'), >>> + 'SurgeSpecweb': [SysConfig('spec-surge-server.rcS', >>> '512MB'), >>> SysConfig('spec-surge-client.rcS', >>> '256MB')], >>> - 'Nhfsstone': [SysConfig('nfs-server-nhfsstone.rcS', '512MB'), >>> + 'Nhfsstone': [SysConfig('nfs-server-nhfsstone.rcS', >>> '512MB'), >>> SysConfig('nfs-client-nhfsstone.rcS')], >>> - 'Nfs': [SysConfig('nfs-server.rcS', '900MB'), >>> + 'Nfs': [SysConfig('nfs-server.rcS', '900MB'), >>> SysConfig('nfs-client-dbench.rcS')], >>> - 'NfsTcp': [SysConfig('nfs-server.rcS', '900MB'), >>> + 'NfsTcp': [SysConfig('nfs-server.rcS', '900MB'), >>> SysConfig('nfs-client-tcp.rcS')], >>> - 'IScsiInitiator': [SysConfig('iscsi-client.rcS', '512MB'), >>> + 'IScsiInitiator': [SysConfig('iscsi-client.rcS', '512MB'), >>> SysConfig('iscsi-server.rcS', '512MB')], >>> - 'IScsiTarget': [SysConfig('iscsi-server.rcS', '512MB'), >>> + 'IScsiTarget': [SysConfig('iscsi-server.rcS', '512MB'), >>> SysConfig('iscsi-client.rcS', '512MB')], >>> - 'Validation': [SysConfig('iscsi-server.rcS', '512MB'), >>> + 'Validation': [SysConfig('iscsi-server.rcS', '512MB'), >>> SysConfig('iscsi-client.rcS', '512MB')], >>> - 'Ping': [SysConfig('ping-server.rcS',), >>> + 'Ping': [SysConfig('ping-server.rcS',), >>> SysConfig('ping-client.rcS')], >>> >>> - 'ValAccDelay': [SysConfig('devtime.rcS', '512MB')], >>> - 'ValAccDelay2': [SysConfig('devtimewmr.rcS', '512MB')], >>> - 'ValMemLat': [SysConfig('micro_memlat.rcS', '512MB')], >>> - 'ValMemLat2MB': [SysConfig('micro_memlat2mb.rcS', '512MB')], >>> - 'ValMemLat8MB': [SysConfig('micro_memlat8mb.rcS', '512MB')], >>> - 'ValMemLat': [SysConfig('micro_memlat8.rcS', '512MB')], >>> - 'ValTlbLat': [SysConfig('micro_tlblat.rcS', '512MB')], >>> - 'ValSysLat': [SysConfig('micro_syscall.rcS', '512MB')], >>> - 'ValCtxLat': [SysConfig('micro_ctx.rcS', '512MB')], >>> - 'ValStream': [SysConfig('micro_stream.rcS', '512MB')], >>> - 'ValStreamScale': [SysConfig('micro_streamscale.rcS', '512MB')], >>> - 'ValStreamCopy': [SysConfig('micro_streamcopy.rcS', '512MB')], >>> + 'ValAccDelay': [SysConfig('devtime.rcS', '512MB')], >>> + 'ValAccDelay2': [SysConfig('devtimewmr.rcS', '512MB')], >>> + 'ValMemLat': [SysConfig('micro_memlat.rcS', '512MB')], >>> + 'ValMemLat2MB': [SysConfig('micro_memlat2mb.rcS', '512MB')], >>> + 'ValMemLat8MB': [SysConfig('micro_memlat8mb.rcS', '512MB')], >>> + 'ValMemLat': [SysConfig('micro_memlat8.rcS', '512MB')], >>> + 'ValTlbLat': [SysConfig('micro_tlblat.rcS', '512MB')], >>> + 'ValSysLat': [SysConfig('micro_syscall.rcS', '512MB')], >>> + 'ValCtxLat': [SysConfig('micro_ctx.rcS', '512MB')], >>> + 'ValStream': [SysConfig('micro_stream.rcS', '512MB')], >>> + 'ValStreamScale': [SysConfig('micro_streamscale.rcS', >>> '512MB')], >>> + 'ValStreamCopy': [SysConfig('micro_streamcopy.rcS', >>> '512MB')], >>> >>> 'MutexTest': [SysConfig('mutex-test.rcS', '128MB')], >>> >>> diff -r cdb571ebb4a8 -r 3af77710f397 src/arch/alpha/aout_machdep.h >>> --- a/src/arch/alpha/aout_machdep.h Tue Sep 09 16:27:17 2008 -0700 >>> +++ b/src/arch/alpha/aout_machdep.h Wed Sep 10 14:26:15 2008 -0400 >>> @@ -36,35 +36,35 @@ >>> /// Funky Alpha 64-bit a.out header used for PAL code. >>> /// >>> struct aout_exechdr { >>> - uint16_t magic; ///< magic number >>> - uint16_t vstamp; ///< version stamp? >>> - uint16_t bldrev; ///< ??? >>> - uint16_t padcell; ///< padding >>> - uint64_t tsize; ///< text segment size >>> - uint64_t dsize; ///< data segment size >>> - uint64_t bsize; ///< bss segment size >>> - uint64_t entry; ///< entry point >>> - uint64_t text_start; ///< text base address >>> - uint64_t data_start; ///< data base address >>> - uint64_t bss_start; ///< bss base address >>> - uint32_t gprmask; ///< GPR mask (unused, AFAIK) >>> - uint32_t fprmask; ///< FPR mask (unused, AFAIK) >>> - uint64_t gp_value; ///< global pointer reg value >>> + uint16_t magic; ///< magic number >>> + uint16_t vstamp; ///< version stamp? >>> + uint16_t bldrev; ///< ??? >>> + uint16_t padcell; ///< padding >>> + uint64_t tsize; ///< text segment size >>> + uint64_t dsize; ///< data segment size >>> + uint64_t bsize; ///< bss segment size >>> + uint64_t entry; ///< entry point >>> + uint64_t text_start; ///< text base address >>> + uint64_t data_start; ///< data base address >>> + uint64_t bss_start; ///< bss base address >>> + uint32_t gprmask; ///< GPR mask (unused, AFAIK) >>> + uint32_t fprmask; ///< FPR mask (unused, AFAIK) >>> + uint64_t gp_value; ///< global pointer reg value >>> }; >>> >>> -#define AOUT_LDPGSZ 8192 >>> +#define AOUT_LDPGSZ 8192 >>> >>> -#define N_GETMAGIC(ex) ((ex).magic) >>> +#define N_GETMAGIC(ex) ((ex).magic) >>> >>> #define N_BADMAX >>> >>> -#define N_TXTADDR(ex) ((ex).text_start) >>> -#define N_DATADDR(ex) ((ex).data_start) >>> -#define N_BSSADDR(ex) ((ex).bss_start) >>> +#define N_TXTADDR(ex) ((ex).text_start) >>> +#define N_DATADDR(ex) ((ex).data_start) >>> +#define N_BSSADDR(ex) ((ex).bss_start) >>> >>> -#define N_TXTOFF(ex) \ >>> +#define N_TXTOFF(ex) \ >>> (N_GETMAGIC(ex) == ZMAGIC ? 0 : sizeof(struct aout_exechdr)) >>> >>> -#define N_DATOFF(ex) N_ALIGN(ex, N_TXTOFF(ex) + (ex).tsize) >>> +#define N_DATOFF(ex) N_ALIGN(ex, N_TXTOFF(ex) + (ex).tsize) >>> >>> #endif /* !__AOUT_MACHDEP_H__*/ >>> diff -r cdb571ebb4a8 -r 3af77710f397 src/arch/alpha/ev5.cc >>> --- a/src/arch/alpha/ev5.cc Tue Sep 09 16:27:17 2008 -0700 >>> +++ b/src/arch/alpha/ev5.cc Wed Sep 10 14:26:15 2008 -0400 >>> @@ -176,7 +176,7 @@ >>> AlphaISA::MiscReg >>> AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc) >>> { >>> - uint64_t retval = 0; // return value, default 0 >>> + uint64_t retval = 0; // return value, default 0 >>> >>> switch (idx) { >>> case AlphaISA::IPR_PALtemp0: >>> diff -r cdb571ebb4a8 -r 3af77710f397 src/arch/alpha/floatregfile.hh >>> --- a/src/arch/alpha/floatregfile.hh Tue Sep 09 16:27:17 2008 -0700 >>> +++ b/src/arch/alpha/floatregfile.hh Wed Sep 10 14:26:15 2008 -0400 >>> @@ -52,8 +52,8 @@ >>> public: >>> >>> union { >>> - uint64_t q[NumFloatRegs]; // integer qword view >>> - double d[NumFloatRegs]; // double-precision floating >>> point view >>> + uint64_t q[NumFloatRegs]; // integer qword view >>> + double d[NumFloatRegs]; // double-precision >>> floating point >>> view >>> }; >>> >>> void serialize(std::ostream &os); >>> diff -r cdb571ebb4a8 -r 3af77710f397 src/arch/alpha/ipr.cc >>> --- a/src/arch/alpha/ipr.cc Tue Sep 09 16:27:17 2008 -0700 >>> +++ b/src/arch/alpha/ipr.cc Wed Sep 10 14:26:15 2008 -0400 >>> @@ -38,89 +38,89 @@ >>> md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs] = >>> { >>> //Write only >>> - RAW_IPR_HWINT_CLR, // H/W interrupt clear register >>> - RAW_IPR_SL_XMIT, // serial line transmit register >>> + RAW_IPR_HWINT_CLR, // H/W interrupt clear register >>> + RAW_IPR_SL_XMIT, // serial line transmit register >>> RAW_IPR_DC_FLUSH, >>> - RAW_IPR_IC_FLUSH, // instruction cache flush control >>> - RAW_IPR_ALT_MODE, // alternate mode register >>> - RAW_IPR_DTB_IA, // DTLB invalidate all register >>> - RAW_IPR_DTB_IAP, // DTLB invalidate all process register >>> - RAW_IPR_ITB_IA, // ITLB invalidate all register >>> - RAW_IPR_ITB_IAP, // ITLB invalidate all process register >>> + RAW_IPR_IC_FLUSH, // instruction cache flush control >>> + RAW_IPR_ALT_MODE, // alternate mode register >>> + RAW_IPR_DTB_IA, // DTLB invalidate all register >>> + RAW_IPR_DTB_IAP, // DTLB invalidate all process >>> register >>> + RAW_IPR_ITB_IA, // ITLB invalidate all register >>> + RAW_IPR_ITB_IAP, // ITLB invalidate all process >>> register >>> >>> //Read only >>> - RAW_IPR_INTID, // interrupt ID register >>> - RAW_IPR_SL_RCV, // serial line receive register >>> - RAW_IPR_MM_STAT, // data MMU fault status register >>> - RAW_IPR_ITB_PTE_TEMP, // ITLB page table entry temp register >>> - RAW_IPR_DTB_PTE_TEMP, // DTLB page table entry temporary >>> register >>> + RAW_IPR_INTID, // interrupt ID register >>> + RAW_IPR_SL_RCV, // serial line receive register >>> + RAW_IPR_MM_STAT, // data MMU fault status register >>> + RAW_IPR_ITB_PTE_TEMP, // ITLB page table entry temp >>> register >>> + RAW_IPR_DTB_PTE_TEMP, // DTLB page table entry temporary >>> register >>> >>> - RAW_IPR_ISR, // interrupt summary register >>> - RAW_IPR_ITB_TAG, // ITLB tag register >>> - RAW_IPR_ITB_PTE, // ITLB page table entry register >>> - RAW_IPR_ITB_ASN, // ITLB address space register >>> - RAW_IPR_ITB_IS, // ITLB invalidate select register >>> - RAW_IPR_SIRR, // software interrupt request register >>> - RAW_IPR_ASTRR, // asynchronous system trap request >>> register >>> - RAW_IPR_ASTER, // asynchronous system trap enable >>> register >>> - RAW_IPR_EXC_ADDR, // exception address register >>> - RAW_IPR_EXC_SUM, // exception summary register >>> - RAW_IPR_EXC_MASK, // exception mask register >>> - RAW_IPR_PAL_BASE, // PAL base address register >>> - RAW_IPR_ICM, // instruction current mode >>> - RAW_IPR_IPLR, // interrupt priority level register >>> - RAW_IPR_IFAULT_VA_FORM, // formatted faulting virtual addr >>> register >>> - RAW_IPR_IVPTBR, // virtual page table base register >>> - RAW_IPR_ICSR, // instruction control and status >>> register >>> - RAW_IPR_IC_PERR_STAT, // inst cache parity error status >>> register >>> - RAW_IPR_PMCTR, // performance counter register >>> + RAW_IPR_ISR, // interrupt summary register >>> + RAW_IPR_ITB_TAG, // ITLB tag register >>> + RAW_IPR_ITB_PTE, // ITLB page table entry register >>> + RAW_IPR_ITB_ASN, // ITLB address space register >>> + RAW_IPR_ITB_IS, // ITLB invalidate select register >>> + RAW_IPR_SIRR, // software interrupt request >>> register >>> + RAW_IPR_ASTRR, // asynchronous system trap >>> request register >>> + RAW_IPR_ASTER, // asynchronous system trap enable >>> register >>> + RAW_IPR_EXC_ADDR, // exception address register >>> + RAW_IPR_EXC_SUM, // exception summary register >>> + RAW_IPR_EXC_MASK, // exception mask register >>> + RAW_IPR_PAL_BASE, // PAL base address register >>> + RAW_IPR_ICM, // instruction current mode >>> + RAW_IPR_IPLR, // interrupt priority level register >>> + RAW_IPR_IFAULT_VA_FORM, // formatted faulting virtual addr >>> register >>> + RAW_IPR_IVPTBR, // virtual page table base register >>> + RAW_IPR_ICSR, // instruction control and status >>> register >>> + RAW_IPR_IC_PERR_STAT, // inst cache parity error status >>> register >>> + RAW_IPR_PMCTR, // performance counter register >>> >>> // PAL temporary registers... >>> // register meanings gleaned from osfpal.s source code >>> - RAW_IPR_PALtemp0, // local scratch >>> - RAW_IPR_PALtemp1, // local scratch >>> - RAW_IPR_PALtemp2, // entUna >>> - RAW_IPR_PALtemp3, // CPU specific impure area pointer >>> - RAW_IPR_PALtemp4, // memory management temp >>> - RAW_IPR_PALtemp5, // memory management temp >>> - RAW_IPR_PALtemp6, // memory management temp >>> - RAW_IPR_PALtemp7, // entIF >>> - RAW_IPR_PALtemp8, // intmask >>> - RAW_IPR_PALtemp9, // entSys >>> - RAW_IPR_PALtemp10, // ?? >>> - RAW_IPR_PALtemp11, // entInt >>> - RAW_IPR_PALtemp12, // entArith >>> - RAW_IPR_PALtemp13, // reserved for platform specific PAL >>> - RAW_IPR_PALtemp14, // reserved for platform specific PAL >>> - RAW_IPR_PALtemp15, // reserved for platform specific PAL >>> - RAW_IPR_PALtemp16, // scratch / whami<7:0> / mces<4:0> >>> - RAW_IPR_PALtemp17, // sysval >>> - RAW_IPR_PALtemp18, // usp >>> - RAW_IPR_PALtemp19, // ksp >>> - RAW_IPR_PALtemp20, // PTBR >>> - RAW_IPR_PALtemp21, // entMM >>> - RAW_IPR_PALtemp22, // kgp >>> - RAW_IPR_PALtemp23, // PCBB >>> + RAW_IPR_PALtemp0, // local scratch >>> + RAW_IPR_PALtemp1, // local scratch >>> + RAW_IPR_PALtemp2, // entUna >>> + RAW_IPR_PALtemp3, // CPU specific impure area pointer >>> + RAW_IPR_PALtemp4, // memory management temp >>> + RAW_IPR_PALtemp5, // memory management temp >>> + RAW_IPR_PALtemp6, // memory management temp >>> + RAW_IPR_PALtemp7, // entIF >>> + RAW_IPR_PALtemp8, // intmask >>> + RAW_IPR_PALtemp9, // entSys >>> + RAW_IPR_PALtemp10, // ?? >>> + RAW_IPR_PALtemp11, // entInt >>> + RAW_IPR_PALtemp12, // entArith >>> + RAW_IPR_PALtemp13, // reserved for platform specific >>> PAL >>> + RAW_IPR_PALtemp14, // reserved for platform specific >>> PAL >>> + RAW_IPR_PALtemp15, // reserved for platform specific >>> PAL >>> + RAW_IPR_PALtemp16, // scratch / whami<7:0> / mces<4:0> >>> + RAW_IPR_PALtemp17, // sysval >>> + RAW_IPR_PALtemp18, // usp >>> + RAW_IPR_PALtemp19, // ksp >>> + RAW_IPR_PALtemp20, // PTBR >>> + RAW_IPR_PALtemp21, // entMM >>> + RAW_IPR_PALtemp22, // kgp >>> + RAW_IPR_PALtemp23, // PCBB >>> >>> - RAW_IPR_DTB_ASN, // DTLB address space number register >>> - RAW_IPR_DTB_CM, // DTLB current mode register >>> - RAW_IPR_DTB_TAG, // DTLB tag register >>> - RAW_IPR_DTB_PTE, // DTLB page table entry register >>> + RAW_IPR_DTB_ASN, // DTLB address space number >>> register >>> + RAW_IPR_DTB_CM, // DTLB current mode register >>> + RAW_IPR_DTB_TAG, // DTLB tag register >>> + RAW_IPR_DTB_PTE, // DTLB page table entry register >>> >>> - RAW_IPR_VA, // fault virtual address register >>> - RAW_IPR_VA_FORM, // formatted virtual address register >>> _______________________________________________ >>> m5-dev mailing list >>> [email protected] >>> http://m5sim.org/mailman/listinfo/m5-dev >>> >>> >> >> >> _______________________________________________ >> m5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/m5-dev >> >> > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
