changeset 03c186e416aa in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=03c186e416aa
description:
O3CPU: Fix thread writeback logic.
Fix the logic in the LSQ that determines if there are any stores to
write back. In the commit stage, check for thread specific writebacks
instead of just any writeback.
diffstat:
2 files changed, 1 insertion(+), 3 deletions(-)
src/cpu/o3/iew.hh | 1 +
src/cpu/o3/lsq_impl.hh | 3 ---
diffs (91 lines):
diff -r c9f52fae6b37 -r 03c186e416aa src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh Fri Sep 26 07:44:06 2008 -0700
+++ b/src/cpu/o3/commit_impl.hh Fri Sep 26 07:44:07 2008 -0700
@@ -814,7 +814,7 @@
// @todo: Make this handle multi-cycle communication between
// commit and IEW.
if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
- !iewStage->hasStoresToWB() && !committedStores[tid]) {
+ !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
checkEmptyROB[tid] = false;
toIEW->commitInfo[tid].usedROB = true;
toIEW->commitInfo[tid].emptyROB = true;
@@ -968,7 +968,7 @@
"instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
head_inst->seqNum, head_inst->readPC());
- if (inst_num > 0 || iewStage->hasStoresToWB()) {
+ if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
DPRINTF(Commit, "Waiting for all stores to writeback.\n");
return false;
}
@@ -983,7 +983,7 @@
return false;
} else if (head_inst->isLoad()) {
- if (inst_num > 0 || iewStage->hasStoresToWB()) {
+ if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
DPRINTF(Commit, "Waiting for all stores to writeback.\n");
return false;
}
@@ -1038,7 +1038,7 @@
DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
head_inst->seqNum, head_inst->readPC());
- if (iewStage->hasStoresToWB() || inst_num > 0) {
+ if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
return false;
}
diff -r c9f52fae6b37 -r 03c186e416aa src/cpu/o3/iew.hh
--- a/src/cpu/o3/iew.hh Fri Sep 26 07:44:06 2008 -0700
+++ b/src/cpu/o3/iew.hh Fri Sep 26 07:44:07 2008 -0700
@@ -207,6 +207,9 @@
/** Returns if the LSQ has any stores to writeback. */
bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
+
+ /** Returns if the LSQ has any stores to writeback. */
+ bool hasStoresToWB(unsigned tid) { return ldstQueue.hasStoresToWB(tid); }
void incrWb(InstSeqNum &sn)
{
diff -r c9f52fae6b37 -r 03c186e416aa src/cpu/o3/lsq_impl.hh
--- a/src/cpu/o3/lsq_impl.hh Fri Sep 26 07:44:06 2008 -0700
+++ b/src/cpu/o3/lsq_impl.hh Fri Sep 26 07:44:07 2008 -0700
@@ -584,17 +584,14 @@
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
- if (threads == end)
- return false;
-
while (threads != end) {
unsigned tid = *threads++;
- if (!hasStoresToWB(tid))
- return false;
+ if (hasStoresToWB(tid))
+ return true;
}
- return true;
+ return false;
}
template<class Impl>
@@ -607,11 +604,11 @@
while (threads != end) {
unsigned tid = *threads++;
- if (!willWB(tid))
- return false;
+ if (willWB(tid))
+ return true;
}
- return true;
+ return false;
}
template<class Impl>
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