changeset d14250d688d2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d14250d688d2
description:
alpha: Clean up namespace usage.
diffstat:
11 files changed, 12 insertions(+), 15 deletions(-)
src/arch/alpha/ev5.hh | 1 -
src/arch/alpha/faults.cc | 2 +-
src/arch/alpha/faults.hh | 2 +-
src/arch/alpha/intregfile.cc | 2 +-
src/arch/alpha/isa/main.isa | 2 +-
src/arch/alpha/pagetable.hh | 2 +-
src/arch/alpha/remote_gdb.cc | 4 ++--
src/arch/alpha/stacktrace.hh | 1 -
src/arch/alpha/system.cc | 1 -
src/arch/alpha/tlb.hh | 1 -
src/arch/alpha/vtophys.cc | 9 +++++----
diffs (truncated from 1356 to 300 lines):
diff -r 8fc3b004b0df -r d14250d688d2 src/arch/alpha/ev5.cc
--- a/src/arch/alpha/ev5.cc Sat Sep 27 21:03:46 2008 -0700
+++ b/src/arch/alpha/ev5.cc Sat Sep 27 21:03:47 2008 -0700
@@ -44,7 +44,7 @@
#include "sim/debug.hh"
#include "sim/sim_exit.hh"
-using namespace AlphaISA;
+namespace AlphaISA {
#if FULL_SYSTEM
@@ -53,14 +53,14 @@
// Machine dependent functions
//
void
-AlphaISA::initCPU(ThreadContext *tc, int cpuId)
+initCPU(ThreadContext *tc, int cpuId)
{
initIPRs(tc, cpuId);
tc->setIntReg(16, cpuId);
tc->setIntReg(0, cpuId);
- AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault;
+ AlphaFault *reset = new ResetFault;
tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect());
tc->setNextPC(tc->readPC() + sizeof(MachInst));
@@ -71,7 +71,7 @@
template <class CPU>
void
-AlphaISA::processInterrupts(CPU *cpu)
+processInterrupts(CPU *cpu)
{
//Check if there are any outstanding interrupts
//Handle the interrupts
@@ -117,7 +117,7 @@
template <class CPU>
void
-AlphaISA::zeroRegisters(CPU *cpu)
+zeroRegisters(CPU *cpu)
{
// Insure ISA semantics
// (no longer very clean due to the change in setIntReg() in the
@@ -126,33 +126,16 @@
cpu->thread->setFloatReg(ZeroReg, 0.0);
}
-Fault
-SimpleThread::hwrei()
+int
+MiscRegFile::getInstAsid()
{
- if (!(readPC() & 0x3))
- return new UnimplementedOpcodeFault;
-
- setNextPC(readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR));
-
- if (!misspeculating()) {
- if (kernelStats)
- kernelStats->hwrei();
- }
-
- // FIXME: XXX check for interrupts? XXX
- return NoFault;
+ return ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
}
int
-AlphaISA::MiscRegFile::getInstAsid()
+MiscRegFile::getDataAsid()
{
- return AlphaISA::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
-}
-
-int
-AlphaISA::MiscRegFile::getDataAsid()
-{
- return AlphaISA::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
+ return DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
}
#endif
@@ -162,90 +145,90 @@
//
//
void
-AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
+initIPRs(ThreadContext *tc, int cpuId)
{
for (int i = 0; i < NumInternalProcRegs; ++i) {
tc->setMiscRegNoEffect(i, 0);
}
- tc->setMiscRegNoEffect(IPR_PAL_BASE, AlphaISA::PalBase);
+ tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
}
-AlphaISA::MiscReg
-AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
+MiscReg
+MiscRegFile::readIpr(int idx, ThreadContext *tc)
{
uint64_t retval = 0; // return value, default 0
switch (idx) {
- case AlphaISA::IPR_PALtemp0:
- case AlphaISA::IPR_PALtemp1:
- case AlphaISA::IPR_PALtemp2:
- case AlphaISA::IPR_PALtemp3:
- case AlphaISA::IPR_PALtemp4:
- case AlphaISA::IPR_PALtemp5:
- case AlphaISA::IPR_PALtemp6:
- case AlphaISA::IPR_PALtemp7:
- case AlphaISA::IPR_PALtemp8:
- case AlphaISA::IPR_PALtemp9:
- case AlphaISA::IPR_PALtemp10:
- case AlphaISA::IPR_PALtemp11:
- case AlphaISA::IPR_PALtemp12:
- case AlphaISA::IPR_PALtemp13:
- case AlphaISA::IPR_PALtemp14:
- case AlphaISA::IPR_PALtemp15:
- case AlphaISA::IPR_PALtemp16:
- case AlphaISA::IPR_PALtemp17:
- case AlphaISA::IPR_PALtemp18:
- case AlphaISA::IPR_PALtemp19:
- case AlphaISA::IPR_PALtemp20:
- case AlphaISA::IPR_PALtemp21:
- case AlphaISA::IPR_PALtemp22:
- case AlphaISA::IPR_PALtemp23:
- case AlphaISA::IPR_PAL_BASE:
+ case IPR_PALtemp0:
+ case IPR_PALtemp1:
+ case IPR_PALtemp2:
+ case IPR_PALtemp3:
+ case IPR_PALtemp4:
+ case IPR_PALtemp5:
+ case IPR_PALtemp6:
+ case IPR_PALtemp7:
+ case IPR_PALtemp8:
+ case IPR_PALtemp9:
+ case IPR_PALtemp10:
+ case IPR_PALtemp11:
+ case IPR_PALtemp12:
+ case IPR_PALtemp13:
+ case IPR_PALtemp14:
+ case IPR_PALtemp15:
+ case IPR_PALtemp16:
+ case IPR_PALtemp17:
+ case IPR_PALtemp18:
+ case IPR_PALtemp19:
+ case IPR_PALtemp20:
+ case IPR_PALtemp21:
+ case IPR_PALtemp22:
+ case IPR_PALtemp23:
+ case IPR_PAL_BASE:
- case AlphaISA::IPR_IVPTBR:
- case AlphaISA::IPR_DC_MODE:
- case AlphaISA::IPR_MAF_MODE:
- case AlphaISA::IPR_ISR:
- case AlphaISA::IPR_EXC_ADDR:
- case AlphaISA::IPR_IC_PERR_STAT:
- case AlphaISA::IPR_DC_PERR_STAT:
- case AlphaISA::IPR_MCSR:
- case AlphaISA::IPR_ASTRR:
- case AlphaISA::IPR_ASTER:
- case AlphaISA::IPR_SIRR:
- case AlphaISA::IPR_ICSR:
- case AlphaISA::IPR_ICM:
- case AlphaISA::IPR_DTB_CM:
- case AlphaISA::IPR_IPLR:
- case AlphaISA::IPR_INTID:
- case AlphaISA::IPR_PMCTR:
+ case IPR_IVPTBR:
+ case IPR_DC_MODE:
+ case IPR_MAF_MODE:
+ case IPR_ISR:
+ case IPR_EXC_ADDR:
+ case IPR_IC_PERR_STAT:
+ case IPR_DC_PERR_STAT:
+ case IPR_MCSR:
+ case IPR_ASTRR:
+ case IPR_ASTER:
+ case IPR_SIRR:
+ case IPR_ICSR:
+ case IPR_ICM:
+ case IPR_DTB_CM:
+ case IPR_IPLR:
+ case IPR_INTID:
+ case IPR_PMCTR:
// no side-effect
retval = ipr[idx];
break;
- case AlphaISA::IPR_CC:
+ case IPR_CC:
retval |= ipr[idx] & ULL(0xffffffff00000000);
retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
break;
- case AlphaISA::IPR_VA:
+ case IPR_VA:
retval = ipr[idx];
break;
- case AlphaISA::IPR_VA_FORM:
- case AlphaISA::IPR_MM_STAT:
- case AlphaISA::IPR_IFAULT_VA_FORM:
- case AlphaISA::IPR_EXC_MASK:
- case AlphaISA::IPR_EXC_SUM:
+ case IPR_VA_FORM:
+ case IPR_MM_STAT:
+ case IPR_IFAULT_VA_FORM:
+ case IPR_EXC_MASK:
+ case IPR_EXC_SUM:
retval = ipr[idx];
break;
- case AlphaISA::IPR_DTB_PTE:
+ case IPR_DTB_PTE:
{
- AlphaISA::TlbEntry &entry
+ TlbEntry &entry
= tc->getDTBPtr()->index(!tc->misspeculating());
retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32;
@@ -259,15 +242,15 @@
break;
// write only registers
- case AlphaISA::IPR_HWINT_CLR:
- case AlphaISA::IPR_SL_XMIT:
- case AlphaISA::IPR_DC_FLUSH:
- case AlphaISA::IPR_IC_FLUSH:
- case AlphaISA::IPR_ALT_MODE:
- case AlphaISA::IPR_DTB_IA:
- case AlphaISA::IPR_DTB_IAP:
- case AlphaISA::IPR_ITB_IA:
- case AlphaISA::IPR_ITB_IAP:
+ case IPR_HWINT_CLR:
+ case IPR_SL_XMIT:
+ case IPR_DC_FLUSH:
+ case IPR_IC_FLUSH:
+ case IPR_ALT_MODE:
+ case IPR_DTB_IA:
+ case IPR_DTB_IAP:
+ case IPR_ITB_IA:
+ case IPR_ITB_IAP:
panic("Tried to read write only register %d\n", idx);
break;
@@ -286,7 +269,7 @@
#endif
void
-AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
+MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
{
uint64_t old;
@@ -294,52 +277,52 @@
return;
switch (idx) {
- case AlphaISA::IPR_PALtemp0:
- case AlphaISA::IPR_PALtemp1:
- case AlphaISA::IPR_PALtemp2:
- case AlphaISA::IPR_PALtemp3:
- case AlphaISA::IPR_PALtemp4:
- case AlphaISA::IPR_PALtemp5:
- case AlphaISA::IPR_PALtemp6:
- case AlphaISA::IPR_PALtemp7:
- case AlphaISA::IPR_PALtemp8:
- case AlphaISA::IPR_PALtemp9:
- case AlphaISA::IPR_PALtemp10:
- case AlphaISA::IPR_PALtemp11:
- case AlphaISA::IPR_PALtemp12:
- case AlphaISA::IPR_PALtemp13:
- case AlphaISA::IPR_PALtemp14:
- case AlphaISA::IPR_PALtemp15:
- case AlphaISA::IPR_PALtemp16:
- case AlphaISA::IPR_PALtemp17:
- case AlphaISA::IPR_PALtemp18:
- case AlphaISA::IPR_PALtemp19:
- case AlphaISA::IPR_PALtemp20:
- case AlphaISA::IPR_PALtemp21:
- case AlphaISA::IPR_PALtemp22:
- case AlphaISA::IPR_PAL_BASE:
- case AlphaISA::IPR_IC_PERR_STAT:
- case AlphaISA::IPR_DC_PERR_STAT:
- case AlphaISA::IPR_PMCTR:
+ case IPR_PALtemp0:
+ case IPR_PALtemp1:
+ case IPR_PALtemp2:
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
