changeset 13592d41f290 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=13592d41f290
description:
gcc: Add extra parens to quell warnings.
Even though we're not incorrect about operator precedence, let's add
some parens in some particularly confusing places to placate GCC 4.3
so that we don't have to turn the warning off. Agreed that this is a
bit of a pain for those users who get the order of operations correct,
but it is likely to prevent bugs in certain cases.
diffstat:
11 files changed, 9 insertions(+), 17 deletions(-)
src/arch/alpha/pagetable.hh | 2 +-
src/arch/alpha/utility.hh | 2 +-
src/arch/mips/dsp.cc | 2 +-
src/arch/mips/isa/decoder.isa | 4 ++--
src/arch/mips/pagetable.hh | 2 +-
src/arch/sparc/isa/formats/mem/util.isa | 4 ----
src/arch/x86/predecoder.cc | 4 ++--
src/base/intmath.hh | 2 --
src/base/random_mt.cc | 2 +-
src/base/stats/text.cc | 1 -
src/dev/terminal.cc | 1 -
diffs (truncated from 411 to 300 lines):
diff -r baeee670d4ce -r 13592d41f290 src/arch/alpha/ev5.hh
--- a/src/arch/alpha/ev5.hh Sat Sep 27 21:03:48 2008 -0700
+++ b/src/arch/alpha/ev5.hh Sat Sep 27 21:03:49 2008 -0700
@@ -80,7 +80,7 @@
inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
inline Addr DTB_PTE_PPN(uint64_t reg)
-{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; }
+{ return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); }
inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }
inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
@@ -90,7 +90,7 @@
inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; }
inline Addr ITB_PTE_PPN(uint64_t reg)
-{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; }
+{ return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); }
inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
diff -r baeee670d4ce -r 13592d41f290 src/arch/alpha/pagetable.hh
--- a/src/arch/alpha/pagetable.hh Sat Sep 27 21:03:48 2008 -0700
+++ b/src/arch/alpha/pagetable.hh Sat Sep 27 21:03:49 2008 -0700
@@ -57,9 +57,9 @@
Addr level3() const
{ return PteAddr(addr >> PageShift); }
Addr level2() const
- { return PteAddr(addr >> NPtePageShift + PageShift); }
+ { return PteAddr(addr >> (NPtePageShift + PageShift)); }
Addr level1() const
- { return PteAddr(addr >> 2 * NPtePageShift + PageShift); }
+ { return PteAddr(addr >> (2 * NPtePageShift + PageShift)); }
};
struct PageTableEntry
diff -r baeee670d4ce -r 13592d41f290 src/arch/alpha/utility.hh
--- a/src/arch/alpha/utility.hh Sat Sep 27 21:03:48 2008 -0700
+++ b/src/arch/alpha/utility.hh Sat Sep 27 21:03:49 2008 -0700
@@ -53,14 +53,14 @@
isCallerSaveIntegerRegister(unsigned int reg)
{
panic("register classification not implemented");
- return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
+ return (reg >= 1 && reg <= 8) || (reg >= 22 && reg <= 25) || reg == 27;
}
inline bool
isCalleeSaveIntegerRegister(unsigned int reg)
{
panic("register classification not implemented");
- return (reg >= 9 && reg <= 15);
+ return reg >= 9 && reg <= 15;
}
inline bool
diff -r baeee670d4ce -r 13592d41f290 src/arch/mips/dsp.cc
--- a/src/arch/mips/dsp.cc Sat Sep 27 21:03:48 2008 -0700
+++ b/src/arch/mips/dsp.cc Sat Sep 27 21:03:49 2008 -0700
@@ -923,10 +923,10 @@
for (int i = 0; i<2; i++) {
r_values[i] =
- dspSaturate((int64_t)b_values[i] >> SIMD_NBITS[SIMD_FMT_QB] - 1,
+ dspSaturate((int64_t)b_values[i] >> (SIMD_NBITS[SIMD_FMT_QB] - 1),
SIMD_FMT_QB, UNSIGNED, &ouflag);
r_values[i + 2] =
- dspSaturate((int64_t)a_values[i] >> SIMD_NBITS[SIMD_FMT_QB] - 1,
+ dspSaturate((int64_t)a_values[i] >> (SIMD_NBITS[SIMD_FMT_QB] - 1),
SIMD_FMT_QB, UNSIGNED, &ouflag);
}
diff -r baeee670d4ce -r 13592d41f290 src/arch/mips/isa/decoder.isa
--- a/src/arch/mips/isa/decoder.isa Sat Sep 27 21:03:48 2008 -0700
+++ b/src/arch/mips/isa/decoder.isa Sat Sep 27 21:03:49 2008 -0700
@@ -416,16 +416,16 @@
Ctrl_Base_DepTag);
break;
case 25:
- data = 0 | fcsr_val &
0xFE000000 >> 24
- | fcsr_val &
0x00800000 >> 23;
+ data = (fcsr_val & 0xFE000000
>> 24)
+ | (fcsr_val & 0x00800000
>> 23);
break;
case 26:
- data = 0 | fcsr_val &
0x0003F07C;
+ data = fcsr_val & 0x0003F07C;
break;
case 28:
- data = 0 | fcsr_val &
0x00000F80
- | fcsr_val &
0x01000000 >> 21
- | fcsr_val &
0x00000003;
+ data = (fcsr_val & 0x00000F80)
+ | (fcsr_val & 0x01000000
>> 21)
+ | (fcsr_val & 0x00000003);
break;
case 31:
data = fcsr_val;
@@ -1963,7 +1963,7 @@
0x0: decode OP_LO {
format IntOp {
0x0: append({{ Rt.uw = (Rt.uw << RD) |
bits(Rs.uw,RD-1,0); }});
- 0x1: prepend({{ Rt.uw = (Rt.uw >> RD) |
(bits(Rs.uw,RD-1,0) << 32-RD); }});
+ 0x1: prepend({{ Rt.uw = (Rt.uw >> RD) |
(bits(Rs.uw, RD - 1, 0) << (32 - RD)); }});
}
}
0x2: decode OP_LO {
@@ -2050,11 +2050,11 @@
format LoadUnalignedMemory {
0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset);
Rt.uw = mem_word << mem_shift |
- Rt.uw & mask(mem_shift);
+ (Rt.uw & mask(mem_shift));
}});
0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset;
- Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) |
- mem_word >> mem_shift;
+ Rt.uw = (Rt.uw & (mask(mem_shift) << (32 -
mem_shift))) |
+ (mem_word >> mem_shift);
}});
}
}
@@ -2069,12 +2069,12 @@
format StoreUnalignedMemory {
0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset);
uint32_t mem_shift = 32 - reg_shift;
- mem_word = mem_word & (mask(reg_shift) << mem_shift) |
- Rt.uw >> reg_shift;
+ mem_word = (mem_word & (mask(reg_shift) << mem_shift))
|
+ (Rt.uw >> reg_shift);
}});
0x6: swr({{ uint32_t reg_shift = 8 * byte_offset;
mem_word = Rt.uw << reg_shift |
- mem_word & (mask(reg_shift));
+ (mem_word & (mask(reg_shift)));
}});
}
format CP0Control {
diff -r baeee670d4ce -r 13592d41f290 src/arch/mips/pagetable.hh
--- a/src/arch/mips/pagetable.hh Sat Sep 27 21:03:48 2008 -0700
+++ b/src/arch/mips/pagetable.hh Sat Sep 27 21:03:49 2008 -0700
@@ -59,9 +59,9 @@
Addr level3() const
{ return MipsISA::PteAddr(addr >> PageShift); }
Addr level2() const
- { return MipsISA::PteAddr(addr >> NPtePageShift + PageShift); }
+ { return MipsISA::PteAddr(addr >> (NPtePageShift + PageShift)); }
Addr level1() const
- { return MipsISA::PteAddr(addr >> 2 * NPtePageShift + PageShift); }
+ { return MipsISA::PteAddr(addr >> (2 * NPtePageShift + PageShift)); }
};
// ITB/DTB page table entry
diff -r baeee670d4ce -r 13592d41f290 src/arch/mips/utility.cc
--- a/src/arch/mips/utility.cc Sat Sep 27 21:03:48 2008 -0700
+++ b/src/arch/mips/utility.cc Sat Sep 27 21:03:49 2008 -0700
@@ -145,7 +145,7 @@
{
int cc_idx = (cc_num == 0) ? 23 : cc_num + 24;
- fcsr = bits(fcsr, 31, cc_idx + 1) << cc_idx + 1 |
+ fcsr = bits(fcsr, 31, cc_idx + 1) << (cc_idx + 1) |
cc_val << cc_idx |
bits(fcsr, cc_idx - 1, 0);
diff -r baeee670d4ce -r 13592d41f290 src/arch/sparc/faults.cc
--- a/src/arch/sparc/faults.cc Sat Sep 27 21:03:48 2008 -0700
+++ b/src/arch/sparc/faults.cc Sat Sep 27 21:03:49 2008 -0700
@@ -546,7 +546,7 @@
doNormalFault(tc, trapType(), true);
getHyperVector(tc, PC, NPC, 2);
} else if (level == Hyperprivileged ||
- level == Privileged && trapType() >= 384) {
+ (level == Privileged && trapType() >= 384)) {
doNormalFault(tc, trapType(), true);
getHyperVector(tc, PC, NPC, trapType());
} else {
diff -r baeee670d4ce -r 13592d41f290 src/arch/sparc/isa/formats/mem/util.isa
--- a/src/arch/sparc/isa/formats/mem/util.isa Sat Sep 27 21:03:48 2008 -0700
+++ b/src/arch/sparc/isa/formats/mem/util.isa Sat Sep 27 21:03:49 2008 -0700
@@ -314,10 +314,11 @@
# are split into ones that are available in priv and hpriv, and
# those that are only available in hpriv
AlternateASIPrivFaultCheck = '''
- if(!bits(Pstate,2,2) && !bits(Hpstate,2,2) &&
!AsiIsUnPriv((ASI)EXT_ASI) ||
- !bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI))
- fault = new PrivilegedAction;
- else if(AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
+ if ((!bits(Pstate,2,2) && !bits(Hpstate,2,2) &&
+ !AsiIsUnPriv((ASI)EXT_ASI)) ||
+ (!bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI)))
+ fault = new PrivilegedAction;
+ else if (AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2))
fault = new PrivilegedAction;
'''
diff -r baeee670d4ce -r 13592d41f290 src/arch/sparc/tlb.cc
--- a/src/arch/sparc/tlb.cc Sat Sep 27 21:03:48 2008 -0700
+++ b/src/arch/sparc/tlb.cc Sat Sep 27 21:03:49 2008 -0700
@@ -562,7 +562,7 @@
asi = (ASI)req->getAsi();
bool implicit = false;
bool hpriv = bits(tlbdata,0,0);
- bool unaligned = (vaddr & size-1);
+ bool unaligned = vaddr & (size - 1);
DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
vaddr, size, asi);
@@ -801,8 +801,8 @@
return new PrivilegedAction;
}
- if (asi == ASI_SWVR_UDB_INTR_W && !write ||
- asi == ASI_SWVR_UDB_INTR_R && write) {
+ if ((asi == ASI_SWVR_UDB_INTR_W && !write) ||
+ (asi == ASI_SWVR_UDB_INTR_R && write)) {
writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
return new DataAccessException;
}
@@ -822,7 +822,7 @@
writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
return new PrivilegedAction;
}
- if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) {
+ if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) {
writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
return new DataAccessException;
}
diff -r baeee670d4ce -r 13592d41f290 src/arch/x86/emulenv.cc
--- a/src/arch/x86/emulenv.cc Sat Sep 27 21:03:48 2008 -0700
+++ b/src/arch/x86/emulenv.cc Sat Sep 27 21:03:49 2008 -0700
@@ -91,7 +91,7 @@
//Figure out what segment to use. This won't be entirely accurate since
//the presence of a displacement is supposed to make the instruction
//default to the data segment.
- if (base != INTREG_RBP && base != INTREG_RSP ||
+ if ((base != INTREG_RBP && base != INTREG_RSP) ||
0/*Has an immediate offset*/) {
seg = SEGMENT_REG_DS;
//Handle any segment override that might have been in the instruction
diff -r baeee670d4ce -r 13592d41f290 src/arch/x86/insts/microop.cc
--- a/src/arch/x86/insts/microop.cc Sat Sep 27 21:03:48 2008 -0700
+++ b/src/arch/x86/insts/microop.cc Sat Sep 27 21:03:49 2008 -0700
@@ -98,7 +98,7 @@
case ConditionTests::SxOF:
return ccflags.sf ^ ccflags.of;
case ConditionTests::SxOvZF:
- return ccflags.sf ^ ccflags.of | ccflags.zf;
+ return (ccflags.sf ^ ccflags.of) | ccflags.zf;
case ConditionTests::False:
return false;
case ConditionTests::NotECF:
@@ -131,7 +131,7 @@
case ConditionTests::NotSxOF:
return !(ccflags.sf ^ ccflags.of);
case ConditionTests::NotSxOvZF:
- return !(ccflags.sf ^ ccflags.of | ccflags.zf);
+ return !((ccflags.sf ^ ccflags.of) | ccflags.zf);
}
panic("Unknown condition: %d\n", condition);
return true;
diff -r baeee670d4ce -r 13592d41f290 src/arch/x86/predecoder.cc
--- a/src/arch/x86/predecoder.cc Sat Sep 27 21:03:48 2008 -0700
+++ b/src/arch/x86/predecoder.cc Sat Sep 27 21:03:49 2008 -0700
@@ -319,17 +319,17 @@
if (emi.mode.submode != SixtyFourBitMode &&
!csAttr.defaultSize) {
//figure out 16 bit displacement size
- if(modRM.mod == 0 && modRM.rm == 6 || modRM.mod == 2)
+ if ((modRM.mod == 0 && modRM.rm == 6) || modRM.mod == 2)
displacementSize = 2;
- else if(modRM.mod == 1)
+ else if (modRM.mod == 1)
displacementSize = 1;
else
displacementSize = 0;
} else {
//figure out 32/64 bit displacement size
- if(modRM.mod == 0 && modRM.rm == 5 || modRM.mod == 2)
+ if ((modRM.mod == 0 && modRM.rm == 5) || modRM.mod == 2)
displacementSize = 4;
- else if(modRM.mod == 1)
+ else if (modRM.mod == 1)
displacementSize = 1;
else
displacementSize = 0;
diff -r baeee670d4ce -r 13592d41f290 src/arch/x86/regfile.cc
--- a/src/arch/x86/regfile.cc Sat Sep 27 21:03:48 2008 -0700
+++ b/src/arch/x86/regfile.cc Sat Sep 27 21:03:49 2008 -0700
@@ -214,7 +214,7 @@
//If we need to fold over the index to match byte semantics, do that.
//Otherwise, just strip off any extra bits and pass it through.
if (reg & (1 << 6))
- return (reg & ~(1 << 6) - 0x4);
+ return (reg & (~(1 << 6) - 0x4));
else
return (reg & ~(1 << 6));
}
diff -r baeee670d4ce -r 13592d41f290 src/base/circlebuf.cc
--- a/src/base/circlebuf.cc Sat Sep 27 21:03:48 2008 -0700
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