changeset 16fe9e6c6e0e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=16fe9e6c6e0e
description:
tests: Kevin fixed how writebacks are handled in SMT and that changed
stats.
diffstat:
3 files changed, 15 insertions(+), 27 deletions(-)
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt | 33
++++------
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr | 3
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout | 6 -
diffs (truncated from 1109 to 300 lines):
diff -r 7f81bb169068 -r 16fe9e6c6e0e
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt Sat Sep
27 21:03:50 2008 -0700
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt Sun Sep
28 14:15:37 2008 -0700
@@ -1,54 +1,54 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 849 #
Number of BTB hits
-global.BPredUnit.BTBLookups 4531 #
Number of BTB lookups
-global.BPredUnit.RASInCorrect 176 #
Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 1493 #
Number of conditional branches incorrect
-global.BPredUnit.condPredicted 2930 #
Number of conditional branches predicted
-global.BPredUnit.lookups 5203 #
Number of BP lookups
-global.BPredUnit.usedRAS 663 #
Number of times the RAS was used to get a target.
-host_inst_rate 79876 #
Simulator instruction rate (inst/s)
-host_mem_usage 198844 #
Number of bytes of host memory used
-host_seconds 0.16 #
Real time elapsed on the host
-host_tick_rate 88938501 #
Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 48 #
Number of conflicting loads.
-memdepunit.memDep.conflictingLoads 19 #
Number of conflicting loads.
-memdepunit.memDep.conflictingStores 32 #
Number of conflicting stores.
-memdepunit.memDep.conflictingStores 7 #
Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2378 #
Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedLoads 2381 #
Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1292 #
Number of stores inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1235 #
Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBHits 854 #
Number of BTB hits
+global.BPredUnit.BTBLookups 4386 #
Number of BTB lookups
+global.BPredUnit.RASInCorrect 172 #
Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 1443 #
Number of conditional branches incorrect
+global.BPredUnit.condPredicted 2855 #
Number of conditional branches predicted
+global.BPredUnit.lookups 5041 #
Number of BP lookups
+global.BPredUnit.usedRAS 646 #
Number of times the RAS was used to get a target.
+host_inst_rate 37318 #
Simulator instruction rate (inst/s)
+host_mem_usage 199092 #
Number of bytes of host memory used
+host_seconds 0.34 #
Real time elapsed on the host
+host_tick_rate 41547100 #
Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 23 #
Number of conflicting loads.
+memdepunit.memDep.conflictingLoads 42 #
Number of conflicting loads.
+memdepunit.memDep.conflictingStores 9 #
Number of conflicting stores.
+memdepunit.memDep.conflictingStores 25 #
Number of conflicting stores.
+memdepunit.memDep.insertedLoads 2327 #
Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedLoads 2333 #
Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 1262 #
Number of stores inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 1249 #
Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 12595 #
Number of instructions simulated
sim_seconds 0.000014 #
Number of seconds simulated
-sim_ticks 14042500 #
Number of ticks simulated
+sim_ticks 14029500 #
Number of ticks simulated
system.cpu.commit.COM:branches 2024 #
Number of branches committed
system.cpu.commit.COM:branches_0 1012 #
Number of branches committed
system.cpu.commit.COM:branches_1 1012 #
Number of branches committed
-system.cpu.commit.COM:bw_lim_events 138 #
number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 158 #
number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 #
number of insts not committed due to BW limits
system.cpu.commit.COM:bw_limited_0 0 #
number of insts not committed due to BW limits
system.cpu.commit.COM:bw_limited_1 0 #
number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist #
Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 22161
+system.cpu.commit.COM:committed_per_cycle.samples 21929
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 16399 7399.94%
- 1 2912 1314.02%
- 2 1246 562.25%
- 3 587 264.88%
- 4 387 174.63%
- 5 231 104.24%
- 6 170 76.71%
- 7 91 41.06%
- 8 138 62.27%
+ 0 16145 7362.40%
+ 1 3000 1368.05%
+ 2 1194 544.48%
+ 3 576 262.67%
+ 4 357 162.80%
+ 5 253 115.37%
+ 6 166 75.70%
+ 7 80 36.48%
+ 8 158 72.05%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:count 12629 #
Number of instructions committed
-system.cpu.commit.COM:count_0 6315 #
Number of instructions committed
-system.cpu.commit.COM:count_1 6314 #
Number of instructions committed
+system.cpu.commit.COM:count_0 6314 #
Number of instructions committed
+system.cpu.commit.COM:count_1 6315 #
Number of instructions committed
system.cpu.commit.COM:loads 2336 #
Number of loads committed
system.cpu.commit.COM:loads_0 1168 #
Number of loads committed
system.cpu.commit.COM:loads_1 1168 #
Number of loads committed
@@ -61,89 +61,89 @@
system.cpu.commit.COM:swp_count 0 #
Number of s/w prefetches committed
system.cpu.commit.COM:swp_count_0 0 #
Number of s/w prefetches committed
system.cpu.commit.COM:swp_count_1 0 #
Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 1089 #
The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 1061 #
The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 12629 #
The number of committed instructions
system.cpu.commit.commitNonSpecStalls 34 #
The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 10184 #
The number of squashed insts skipped by commit
-system.cpu.committedInsts_0 6298 #
Number of Instructions Simulated
-system.cpu.committedInsts_1 6297 #
Number of Instructions Simulated
+system.cpu.commit.commitSquashedInsts 9861 #
The number of squashed insts skipped by commit
+system.cpu.committedInsts_0 6297 #
Number of Instructions Simulated
+system.cpu.committedInsts_1 6298 #
Number of Instructions Simulated
system.cpu.committedInsts_total 12595 #
Number of Instructions Simulated
-system.cpu.cpi_0 4.459511 #
CPI: Cycles Per Instruction
-system.cpu.cpi_1 4.460219 #
CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.229933 #
CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 3753 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses_0 3753 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency_0 35747.734139
# average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 37101.010101
# average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 3422 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_hits_0 3422 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 11832500 #
number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency_0 11832500 #
number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate_0 0.088196 #
miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 331 #
number of ReadReq misses
-system.cpu.dcache.ReadReq_misses_0 331 #
number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 133 #
number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits_0 133 #
number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 7346000
# number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency_0 7346000
# number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.052758
# mshr miss rate for ReadReq accesses
+system.cpu.cpi_0 4.456090 #
CPI: Cycles Per Instruction
+system.cpu.cpi_1 4.455383 #
CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.227868 #
CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 3746 #
number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses_0 3746 #
number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency_0 35521.212121
# average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 36972.222222
# average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 3416 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_hits_0 3416 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 11722000 #
number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency_0 11722000 #
number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate_0 0.088094 #
miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 330 #
number of ReadReq misses
+system.cpu.dcache.ReadReq_misses_0 330 #
number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 132 #
number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits_0 132 #
number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 7320500
# number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency_0 7320500
# number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.052856
# mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 198 #
number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses_0 198 #
number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 1724 #
number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses_0 1724 #
number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency_0 33945.394737
# average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 36212.643678
# average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency_0 33638.157895
# average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 35974.137931
# average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 964 #
number of WriteReq hits
system.cpu.dcache.WriteReq_hits_0 964 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 25798500 #
number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency_0 25798500 #
number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 25565000 #
number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency_0 25565000 #
number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate_0 0.440835 #
miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 760 #
number of WriteReq misses
system.cpu.dcache.WriteReq_misses_0 760 #
number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 586 #
number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits_0 586 #
number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 6301000
# number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency_0 6301000
# number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 6259500
# number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency_0 6259500
# number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.100928
# mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 174 #
number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses_0 174 #
number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>
# average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>
# average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 12.933140 #
Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 12.915698 #
Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 #
number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 #
number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 #
number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0
# number of cycles access was blocked
system.cpu.dcache.cache_copies 0 #
number of cache copies performed
-system.cpu.dcache.demand_accesses 5477 #
number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses_0 5477 #
number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses 5470 #
number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses_0 5470 #
number of demand (read+write) accesses
system.cpu.dcache.demand_accesses_1 0 #
number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency <err: div-0> #
average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency_0 34492.208983
# average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency_0 34208.256881
# average overall miss latency
system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0>
# average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0>
# average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency_0 36685.483871
# average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency_0 36505.376344
# average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0>
# average overall mshr miss latency
-system.cpu.dcache.demand_hits 4386 #
number of demand (read+write) hits
-system.cpu.dcache.demand_hits_0 4386 #
number of demand (read+write) hits
+system.cpu.dcache.demand_hits 4380 #
number of demand (read+write) hits
+system.cpu.dcache.demand_hits_0 4380 #
number of demand (read+write) hits
system.cpu.dcache.demand_hits_1 0 #
number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 37631000 #
number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency_0 37631000 #
number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 37287000 #
number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency_0 37287000 #
number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency_1 0 #
number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate <err: div-0> #
miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate_0 0.199197 #
miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate_0 0.199269 #
miss rate for demand accesses
system.cpu.dcache.demand_miss_rate_1 <err: div-0> #
miss rate for demand accesses
-system.cpu.dcache.demand_misses 1091 #
number of demand (read+write) misses
-system.cpu.dcache.demand_misses_0 1091 #
number of demand (read+write) misses
+system.cpu.dcache.demand_misses 1090 #
number of demand (read+write) misses
+system.cpu.dcache.demand_misses_0 1090 #
number of demand (read+write) misses
system.cpu.dcache.demand_misses_1 0 #
number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 719 #
number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits_0 719 #
number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits 718 #
number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits_0 718 #
number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits_1 0 #
number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 13647000
# number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency_0 13647000
# number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 13580000
# number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency_0 13580000
# number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency_1 0
# number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate <err: div-0> #
mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate_0 0.067920 #
mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate_0 0.068007 #
mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> #
mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 372 #
number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses_0 372 #
number of demand (read+write) MSHR misses
@@ -153,38 +153,38 @@
system.cpu.dcache.mshr_cap_events_0 0 #
number of times MSHR cap was activated
system.cpu.dcache.mshr_cap_events_1 0 #
number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 5477 #
number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses_0 5477 #
number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses 5470 #
number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses_0 5470 #
number of overall (read+write) accesses
system.cpu.dcache.overall_accesses_1 0 #
number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency <err: div-0>
# average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency_0 34492.208983
# average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency_0 34208.256881
# average overall miss latency
system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0>
# average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0>
# average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency_0 36685.483871
# average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency_0 36505.376344
# average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0>
# average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>
# average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0>
# average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0>
# average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 4386 #
number of overall hits
-system.cpu.dcache.overall_hits_0 4386 #
number of overall hits
+system.cpu.dcache.overall_hits 4380 #
number of overall hits
+system.cpu.dcache.overall_hits_0 4380 #
number of overall hits
system.cpu.dcache.overall_hits_1 0 #
number of overall hits
-system.cpu.dcache.overall_miss_latency 37631000 #
number of overall miss cycles
-system.cpu.dcache.overall_miss_latency_0 37631000 #
number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 37287000 #
number of overall miss cycles
+system.cpu.dcache.overall_miss_latency_0 37287000 #
number of overall miss cycles
system.cpu.dcache.overall_miss_latency_1 0 #
number of overall miss cycles
system.cpu.dcache.overall_miss_rate <err: div-0> #
miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate_0 0.199197 #
miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate_0 0.199269 #
miss rate for overall accesses
system.cpu.dcache.overall_miss_rate_1 <err: div-0> #
miss rate for overall accesses
-system.cpu.dcache.overall_misses 1091 #
number of overall misses
-system.cpu.dcache.overall_misses_0 1091 #
number of overall misses
+system.cpu.dcache.overall_misses 1090 #
number of overall misses
+system.cpu.dcache.overall_misses_0 1090 #
number of overall misses
system.cpu.dcache.overall_misses_1 0 #
number of overall misses
-system.cpu.dcache.overall_mshr_hits 719 #
number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits_0 719 #
number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits 718 #
number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits_0 718 #
number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits_1 0 #
number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 13647000
# number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency_0 13647000
# number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 13580000
# number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency_0 13580000
# number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency_1 0
# number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate <err: div-0> #
mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate_0 0.067920
# mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate_0 0.068007
# mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0>
# mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 372 #
number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses_0 372 #
number of overall MSHR misses
@@ -211,157 +211,157 @@
system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
system.cpu.dcache.soft_prefetch_mshr_full_0 0
# number of mshr full events for SW prefetching instrutions
system.cpu.dcache.soft_prefetch_mshr_full_1 0
# number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 220.225325 #
Cycle average of tags in use
-system.cpu.dcache.total_refs 4449 #
Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 218.241072 #
Cycle average of tags in use
+system.cpu.dcache.total_refs 4443 #
Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 #
number of writebacks
system.cpu.dcache.writebacks_0 0 #
number of writebacks
system.cpu.dcache.writebacks_1 0 #
number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 4888 #
Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 421 #
Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 556 #
Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 26407 #
Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 32471 #
Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 4675 #
Number of cycles decode is running
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
