changeset 6da7a58b0bc8 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6da7a58b0bc8
description:
eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
diffstat:
37 files changed, 32 insertions(+), 54 deletions(-)
src/arch/alpha/regfile.cc | 2 ++
src/arch/mips/regfile/regfile.hh | 1 +
src/arch/sparc/miscregfile.cc | 1 -
src/arch/sparc/miscregfile.hh | 2 +-
src/arch/sparc/regfile.cc | 5 +++--
src/arch/sparc/regfile.hh | 2 --
src/arch/sparc/ua2005.cc | 2 +-
src/arch/x86/miscregfile.hh | 2 --
src/arch/x86/regfile.cc | 1 -
src/cpu/base.cc | 5 +----
src/cpu/cpuevent.hh | 1 -
src/cpu/memtest/memtest.hh | 1 +
src/cpu/o3/cpu.hh | 2 +-
src/cpu/o3/inst_queue_impl.hh | 2 --
src/cpu/simple/timing.hh | 1 -
src/dev/alpha/tsunami_io.cc | 5 +++--
src/dev/alpha/tsunami_io.hh | 2 +-
src/dev/etherbus.hh | 1 -
src/dev/ethertap.hh | 1 -
src/dev/i8254xGBe.hh | 2 +-
src/dev/intel_8254_timer.cc | 4 +---
src/dev/intel_8254_timer.hh | 3 +++
src/dev/mc146818.cc | 2 --
src/dev/ns_gige.cc | 1 -
src/dev/pcidev.cc | 1 -
src/dev/sinic.cc | 1 -
src/mem/bridge.hh | 2 --
src/mem/bus.cc | 6 ++++--
src/mem/tport.hh | 1 -
src/python/m5/main.py | 2 +-
src/sim/debug.cc | 2 +-
src/sim/sim_events.cc | 3 +++
src/sim/sim_events.hh | 6 +-----
src/sim/sim_exit.hh | 4 ----
src/sim/sim_object_params.hh | 2 ++
src/sim/simulate.cc | 2 --
src/sim/stat_control.cc | 3 ---
diffs (truncated from 2573 to 300 lines):
diff -r b194a80157e2 -r 6da7a58b0bc8 src/arch/alpha/regfile.cc
--- a/src/arch/alpha/regfile.cc Thu Oct 09 04:58:23 2008 -0700
+++ b/src/arch/alpha/regfile.cc Thu Oct 09 04:58:24 2008 -0700
@@ -33,10 +33,12 @@
#include "arch/alpha/regfile.hh"
#include "cpu/thread_context.hh"
+using namespace std;
+
namespace AlphaISA {
void
-RegFile::serialize(std::ostream &os)
+RegFile::serialize(EventManager *em, ostream &os)
{
intRegFile.serialize(os);
floatRegFile.serialize(os);
@@ -49,7 +51,7 @@
}
void
-RegFile::unserialize(Checkpoint *cp, const std::string §ion)
+RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion)
{
intRegFile.unserialize(cp, section);
floatRegFile.unserialize(cp, section);
diff -r b194a80157e2 -r 6da7a58b0bc8 src/arch/alpha/regfile.hh
--- a/src/arch/alpha/regfile.hh Thu Oct 09 04:58:23 2008 -0700
+++ b/src/arch/alpha/regfile.hh Thu Oct 09 04:58:24 2008 -0700
@@ -43,6 +43,7 @@
//XXX These should be implemented by someone who knows the alpha stuff better
class Checkpoint;
+class EventManager;
class ThreadContext;
namespace AlphaISA {
@@ -202,8 +203,9 @@
intRegFile.setReg(intReg, val);
}
- void serialize(std::ostream &os);
- void unserialize(Checkpoint *cp, const std::string §ion);
+ void serialize(EventManager *em, std::ostream &os);
+ void unserialize(EventManager *em, Checkpoint *cp,
+ const std::string §ion);
void
changeContext(RegContextParam param, RegContextVal val)
diff -r b194a80157e2 -r 6da7a58b0bc8 src/arch/mips/regfile/misc_regfile.cc
--- a/src/arch/mips/regfile/misc_regfile.cc Thu Oct 09 04:58:23 2008 -0700
+++ b/src/arch/mips/regfile/misc_regfile.cc Thu Oct 09 04:58:24 2008 -0700
@@ -567,7 +567,7 @@
//schedule UPDATE
CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
- cp0_event->schedule(curTick + cpu->ticks(delay));
+ cpu->schedule(cp0_event, curTick + cpu->ticks(delay));
}
}
@@ -601,8 +601,7 @@
}
MiscRegFile::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type)
- : Event(&mainEventQueue, CPU_Tick_Pri), cp0(_cp0), cpu(_cpu),
- cp0EventType(e_type)
+ : Event(CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type)
{ }
void
@@ -627,10 +626,7 @@
void
MiscRegFile::CP0Event::scheduleEvent(int delay)
{
- if (squashed())
- reschedule(curTick + cpu->ticks(delay));
- else if (!scheduled())
- schedule(curTick + cpu->ticks(delay));
+ cpu->reschedule(this, curTick + cpu->ticks(delay), true);
}
void
diff -r b194a80157e2 -r 6da7a58b0bc8 src/arch/mips/regfile/regfile.cc
--- a/src/arch/mips/regfile/regfile.cc Thu Oct 09 04:58:23 2008 -0700
+++ b/src/arch/mips/regfile/regfile.cc Thu Oct 09 04:58:24 2008 -0700
@@ -193,7 +193,7 @@
}
void
-RegFile::serialize(std::ostream &os)
+RegFile::serialize(EventManager *em, std::ostream &os)
{
intRegFile.serialize(os);
//SERIALIZE_ARRAY(floatRegFile, NumFloatRegs);
@@ -207,7 +207,8 @@
}
void
-RegFile::unserialize(Checkpoint *cp, const std::string §ion)
+RegFile::unserialize(EventManager *em, Checkpoint *cp,
+ const std::string §ion)
{
intRegFile.unserialize(cp, section);
//UNSERIALIZE_ARRAY(floatRegFile);
diff -r b194a80157e2 -r 6da7a58b0bc8 src/arch/mips/regfile/regfile.hh
--- a/src/arch/mips/regfile/regfile.hh Thu Oct 09 04:58:23 2008 -0700
+++ b/src/arch/mips/regfile/regfile.hh Thu Oct 09 04:58:24 2008 -0700
@@ -41,8 +41,9 @@
//#include "cpu/base.hh"
#include "sim/faults.hh"
+class BaseCPU;
class Checkpoint;
-class BaseCPU;
+class EventManager;
namespace MipsISA
{
@@ -99,8 +100,9 @@
Addr readNextNPC();
void setNextNPC(Addr val);
- void serialize(std::ostream &os);
- void unserialize(Checkpoint *cp, const std::string §ion);
+ void serialize(EventManager *em, std::ostream &os);
+ void unserialize(EventManager *em, Checkpoint *cp,
+ const std::string §ion);
void changeContext(RegContextParam param, RegContextVal val)
{
diff -r b194a80157e2 -r 6da7a58b0bc8 src/arch/sparc/miscregfile.cc
--- a/src/arch/sparc/miscregfile.cc Thu Oct 09 04:58:23 2008 -0700
+++ b/src/arch/sparc/miscregfile.cc Thu Oct 09 04:58:24 2008 -0700
@@ -593,7 +593,8 @@
setRegNoEffect(miscReg, new_val);
}
-void MiscRegFile::serialize(std::ostream & os)
+void
+MiscRegFile::serialize(EventManager *em, std::ostream &os)
{
SERIALIZE_SCALAR(asi);
SERIALIZE_SCALAR(tick);
@@ -670,7 +671,9 @@
#endif
}
-void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
+void
+MiscRegFile::unserialize(EventManager *em, Checkpoint *cp,
+ const string §ion)
{
UNSERIALIZE_SCALAR(asi);
UNSERIALIZE_SCALAR(tick);
@@ -729,15 +732,15 @@
if (tick_cmp) {
tickCompare = new TickCompareEvent(this, tc);
- tickCompare->schedule(tick_cmp);
+ em->schedule(tickCompare, tick_cmp);
}
if (stick_cmp) {
sTickCompare = new STickCompareEvent(this, tc);
- sTickCompare->schedule(stick_cmp);
+ em->schedule(sTickCompare, stick_cmp);
}
if (hstick_cmp) {
hSTickCompare = new HSTickCompareEvent(this, tc);
- hSTickCompare->schedule(hstick_cmp);
+ em->schedule(hSTickCompare, hstick_cmp);
}
}
}
diff -r b194a80157e2 -r 6da7a58b0bc8 src/arch/sparc/miscregfile.hh
--- a/src/arch/sparc/miscregfile.hh Thu Oct 09 04:58:23 2008 -0700
+++ b/src/arch/sparc/miscregfile.hh Thu Oct 09 04:58:24 2008 -0700
@@ -288,9 +288,10 @@
return priContext | (uint32_t)partId << 13;
}
- void serialize(std::ostream & os);
+ void serialize(EventManager *em, std::ostream & os);
- void unserialize(Checkpoint * cp, const std::string & section);
+ void unserialize(EventManager *em, Checkpoint *cp,
+ const std::string & section);
void copyMiscRegs(ThreadContext * tc);
diff -r b194a80157e2 -r 6da7a58b0bc8 src/arch/sparc/regfile.cc
--- a/src/arch/sparc/regfile.cc Thu Oct 09 04:58:23 2008 -0700
+++ b/src/arch/sparc/regfile.cc Thu Oct 09 04:58:24 2008 -0700
@@ -219,21 +219,23 @@
//return intRegFile.flattenIndex(reg);
}
-void RegFile::serialize(std::ostream &os)
+void
+RegFile::serialize(EventManager *em, ostream &os)
{
intRegFile.serialize(os);
floatRegFile.serialize(os);
- miscRegFile.serialize(os);
+ miscRegFile.serialize(em, os);
SERIALIZE_SCALAR(pc);
SERIALIZE_SCALAR(npc);
SERIALIZE_SCALAR(nnpc);
}
-void RegFile::unserialize(Checkpoint *cp, const std::string §ion)
+void
+RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion)
{
intRegFile.unserialize(cp, section);
floatRegFile.unserialize(cp, section);
- miscRegFile.unserialize(cp, section);
+ miscRegFile.unserialize(em, cp, section);
UNSERIALIZE_SCALAR(pc);
UNSERIALIZE_SCALAR(npc);
UNSERIALIZE_SCALAR(nnpc);
diff -r b194a80157e2 -r 6da7a58b0bc8 src/arch/sparc/regfile.hh
--- a/src/arch/sparc/regfile.hh Thu Oct 09 04:58:23 2008 -0700
+++ b/src/arch/sparc/regfile.hh Thu Oct 09 04:58:24 2008 -0700
@@ -112,8 +112,9 @@
void setIntReg(int intReg, const IntReg &val);
- void serialize(std::ostream &os);
- void unserialize(Checkpoint *cp, const std::string §ion);
+ void serialize(EventManager *em, std::ostream &os);
+ void unserialize(EventManager *em, Checkpoint *cp,
+ const std::string §ion);
public:
diff -r b194a80157e2 -r 6da7a58b0bc8 src/arch/sparc/ua2005.cc
--- a/src/arch/sparc/ua2005.cc Thu Oct 09 04:58:23 2008 -0700
+++ b/src/arch/sparc/ua2005.cc Thu Oct 09 04:58:24 2008 -0700
@@ -84,12 +84,12 @@
tickCompare = new TickCompareEvent(this, tc);
setRegNoEffect(miscReg, val);
if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled())
- tickCompare->deschedule();
+ cpu->deschedule(tickCompare);
time = (tick_cmpr & mask(63)) - (tick & mask(63));
if (!(tick_cmpr & ~mask(63)) && time > 0) {
if (tickCompare->scheduled())
- tickCompare->deschedule();
- tickCompare->schedule(time * cpu->ticks(1));
+ cpu->deschedule(tickCompare);
+ cpu->schedule(tickCompare, curTick + time * cpu->ticks(1));
}
panic("writing to TICK compare register %#X\n", val);
break;
@@ -99,13 +99,13 @@
sTickCompare = new STickCompareEvent(this, tc);
setRegNoEffect(miscReg, val);
if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
- sTickCompare->deschedule();
+ cpu->deschedule(sTickCompare);
time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
cpu->instCount();
if (!(stick_cmpr & ~mask(63)) && time > 0) {
if (sTickCompare->scheduled())
- sTickCompare->deschedule();
- sTickCompare->schedule(time * cpu->ticks(1) + curTick);
+ cpu->deschedule(sTickCompare);
+ cpu->schedule(sTickCompare, curTick + time * cpu->ticks(1));
}
DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
break;
@@ -169,13 +169,13 @@
hSTickCompare = new HSTickCompareEvent(this, tc);
setRegNoEffect(miscReg, val);
if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
- hSTickCompare->deschedule();
+ cpu->deschedule(hSTickCompare);
time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
cpu->instCount();
if (!(hstick_cmpr & ~mask(63)) && time > 0) {
if (hSTickCompare->scheduled())
- hSTickCompare->deschedule();
- hSTickCompare->schedule(curTick + time * cpu->ticks(1));
+ cpu->deschedule(hSTickCompare);
+ cpu->schedule(hSTickCompare, curTick + time * cpu->ticks(1));
}
DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
break;
@@ -296,12 +296,14 @@
void
MiscRegFile::processSTickCompare(ThreadContext *tc)
{
+ BaseCPU *cpu = tc->getCpuPtr();
+
// since our microcode instructions take two cycles we need to check if
// we're actually at the correct cycle or we need to wait a little while
// more
int ticks;
ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
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