changeset 0e1e9c186769 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=0e1e9c186769
description:
SimObjects: Clean up handling of C++ namespaces.
Make them easier to express by only having the cxx_type parameter which
has the full namespace name, and drop the cxx_namespace thing.
Add support for multiple levels of namespace.
diffstat:
7 files changed, 8 insertions(+), 15 deletions(-)
src/SConscript | 9 +++++----
src/arch/alpha/AlphaTLB.py | 4 +---
src/arch/mips/MipsTLB.py | 3 +--
src/arch/sparc/SparcTLB.py | 4 +---
src/arch/x86/X86TLB.py | 1 -
src/arch/x86/bios/E820.py | 1 -
src/dev/Ethernet.py | 1 -
diffs (truncated from 356 to 300 lines):
diff -r 6782d007ca45 -r 0e1e9c186769 src/SConscript
--- a/src/SConscript Thu Oct 09 22:19:38 2008 -0700
+++ b/src/SConscript Thu Oct 09 22:19:39 2008 -0700
@@ -531,23 +531,24 @@
print >>out, decl
continue
+ class_path = obj.cxx_class.split('::')
+ class_path.reverse()
+ classname = class_path[0]
+ namespaces = class_path[1:]
+
code = ''
- base = obj.get_base()
-
code += '// stop swig from creating/wrapping default ctor/dtor\n'
- code += '%%nodefault %s;\n' % obj.cxx_class
- code += 'class %s ' % obj.cxx_class
- if base:
- code += ': public %s' % base
+ code += '%%nodefault %s;\n' % classname
+ code += 'class %s ' % classname
+ if obj._base:
+ code += ': public %s' % obj._base.cxx_class
code += ' {};\n'
- klass = obj.cxx_class;
- if hasattr(obj, 'cxx_namespace'):
- new_code = 'namespace %s {\n' % obj.cxx_namespace
+ for ns in namespaces:
+ new_code = 'namespace %s {\n' % ns
new_code += code
new_code += '}\n'
code = new_code
- klass = '%s::%s' % (obj.cxx_namespace, klass)
print >>out, code
diff -r 6782d007ca45 -r 0e1e9c186769 src/arch/alpha/AlphaTLB.py
--- a/src/arch/alpha/AlphaTLB.py Thu Oct 09 22:19:38 2008 -0700
+++ b/src/arch/alpha/AlphaTLB.py Thu Oct 09 22:19:39 2008 -0700
@@ -35,14 +35,10 @@
class AlphaDTB(AlphaTLB):
type = 'AlphaDTB'
- cxx_namespace = 'AlphaISA'
- cxx_class = 'DTB'
-
+ cxx_class = 'AlphaISA::DTB'
size = 64
class AlphaITB(AlphaTLB):
type = 'AlphaITB'
- cxx_namespace = 'AlphaISA'
- cxx_class = 'ITB'
-
+ cxx_class = 'AlphaISA::ITB'
size = 48
diff -r 6782d007ca45 -r 0e1e9c186769 src/arch/mips/MipsTLB.py
--- a/src/arch/mips/MipsTLB.py Thu Oct 09 22:19:38 2008 -0700
+++ b/src/arch/mips/MipsTLB.py Thu Oct 09 22:19:39 2008 -0700
@@ -39,19 +39,16 @@
class MipsDTB(MipsTLB):
type = 'MipsDTB'
- cxx_namespace = 'MipsISA'
- cxx_class = 'DTB'
+ cxx_class = 'MipsISA::DTB'
size = 64
class MipsITB(MipsTLB):
type = 'MipsITB'
- cxx_namespace = 'MipsISA'
- cxx_class = 'ITB'
+ cxx_class = 'MipsISA::ITB'
size = 64
class MipsUTB(MipsTLB):
type = 'MipsUTB'
- cxx_namespace = 'MipsISA'
- cxx_class = 'UTB'
+ cxx_class = 'MipsISA::UTB'
size = 64
diff -r 6782d007ca45 -r 0e1e9c186769 src/arch/sparc/SparcTLB.py
--- a/src/arch/sparc/SparcTLB.py Thu Oct 09 22:19:38 2008 -0700
+++ b/src/arch/sparc/SparcTLB.py Thu Oct 09 22:19:39 2008 -0700
@@ -35,14 +35,10 @@
class SparcDTB(SparcTLB):
type = 'SparcDTB'
- cxx_namespace = 'SparcISA'
- cxx_class = 'DTB'
-
+ cxx_class = 'SparcISA::DTB'
size = 64
class SparcITB(SparcTLB):
type = 'SparcITB'
- cxx_namespace = 'SparcISA'
- cxx_class = 'ITB'
-
+ cxx_class = 'SparcISA::ITB'
size = 64
diff -r 6782d007ca45 -r 0e1e9c186769 src/arch/x86/X86TLB.py
--- a/src/arch/x86/X86TLB.py Thu Oct 09 22:19:38 2008 -0700
+++ b/src/arch/x86/X86TLB.py Thu Oct 09 22:19:39 2008 -0700
@@ -62,8 +62,7 @@
if build_env['FULL_SYSTEM']:
class X86PagetableWalker(MemObject):
type = 'X86PagetableWalker'
- cxx_namespace = 'X86ISA'
- cxx_class = 'Walker'
+ cxx_class = 'X86ISA::Walker'
port = Port("Port for the hardware table walker")
system = Param.System(Parent.any, "system object")
@@ -77,14 +76,10 @@
class X86DTB(X86TLB):
type = 'X86DTB'
- cxx_namespace = 'X86ISA'
- cxx_class = 'DTB'
-
+ cxx_class = 'X86ISA::DTB'
size = 64
class X86ITB(X86TLB):
type = 'X86ITB'
- cxx_namespace = 'X86ISA'
- cxx_class = 'ITB'
-
+ cxx_class = 'X86ISA::ITB'
size = 64
diff -r 6782d007ca45 -r 0e1e9c186769 src/arch/x86/bios/E820.py
--- a/src/arch/x86/bios/E820.py Thu Oct 09 22:19:38 2008 -0700
+++ b/src/arch/x86/bios/E820.py Thu Oct 09 22:19:39 2008 -0700
@@ -58,8 +58,7 @@
class X86E820Entry(SimObject):
type = 'X86E820Entry'
- cxx_namespace = 'X86ISA'
- cxx_class = 'E820Entry'
+ cxx_class = 'X86ISA::E820Entry'
addr = Param.Addr(0, 'address of the beginning of the region')
size = Param.MemorySize('0B', 'size of the region')
@@ -67,7 +66,6 @@
class X86E820Table(SimObject):
type = 'X86E820Table'
- cxx_namespace = 'X86ISA'
- cxx_class = 'E820Table'
+ cxx_class = 'X86ISA::E820Table'
entries = VectorParam.X86E820Entry([], 'entries for the e820 table')
diff -r 6782d007ca45 -r 0e1e9c186769 src/cpu/ExeTracer.py
--- a/src/cpu/ExeTracer.py Thu Oct 09 22:19:38 2008 -0700
+++ b/src/cpu/ExeTracer.py Thu Oct 09 22:19:39 2008 -0700
@@ -32,5 +32,4 @@
class ExeTracer(InstTracer):
type = 'ExeTracer'
- cxx_namespace = 'Trace'
- cxx_class = 'ExeTracer'
+ cxx_class = 'Trace::ExeTracer'
diff -r 6782d007ca45 -r 0e1e9c186769 src/cpu/IntelTrace.py
--- a/src/cpu/IntelTrace.py Thu Oct 09 22:19:38 2008 -0700
+++ b/src/cpu/IntelTrace.py Thu Oct 09 22:19:39 2008 -0700
@@ -32,5 +32,4 @@
class IntelTrace(InstTracer):
type = 'IntelTrace'
- cxx_namespace = 'Trace'
- cxx_class = 'IntelTrace'
+ cxx_class = 'Trace::IntelTrace'
diff -r 6782d007ca45 -r 0e1e9c186769 src/cpu/LegionTrace.py
--- a/src/cpu/LegionTrace.py Thu Oct 09 22:19:38 2008 -0700
+++ b/src/cpu/LegionTrace.py Thu Oct 09 22:19:39 2008 -0700
@@ -32,5 +32,4 @@
class LegionTrace(InstTracer):
type = 'LegionTrace'
- cxx_namespace = 'Trace'
- cxx_class = 'LegionTrace'
+ cxx_class = 'Trace::LegionTrace'
diff -r 6782d007ca45 -r 0e1e9c186769 src/cpu/NativeTrace.py
--- a/src/cpu/NativeTrace.py Thu Oct 09 22:19:38 2008 -0700
+++ b/src/cpu/NativeTrace.py Thu Oct 09 22:19:39 2008 -0700
@@ -32,5 +32,4 @@
class NativeTrace(InstTracer):
type = 'NativeTrace'
- cxx_namespace = 'Trace'
- cxx_class = 'NativeTrace'
+ cxx_class = 'Trace::NativeTrace'
diff -r 6782d007ca45 -r 0e1e9c186769 src/dev/Ethernet.py
--- a/src/dev/Ethernet.py Thu Oct 09 22:19:38 2008 -0700
+++ b/src/dev/Ethernet.py Thu Oct 09 22:19:39 2008 -0700
@@ -160,8 +160,7 @@
class Sinic(EtherDevBase):
type = 'Sinic'
- cxx_namespace = 'Sinic'
- cxx_class = 'Device'
+ cxx_class = 'Sinic::Device'
rx_max_copy = Param.MemorySize('1514B', "rx max copy")
tx_max_copy = Param.MemorySize('16kB', "tx max copy")
diff -r 6782d007ca45 -r 0e1e9c186769 src/python/m5/SimObject.py
--- a/src/python/m5/SimObject.py Thu Oct 09 22:19:38 2008 -0700
+++ b/src/python/m5/SimObject.py Thu Oct 09 22:19:39 2008 -0700
@@ -123,7 +123,6 @@
class MetaSimObject(type):
# Attributes that can be set only at initialization time
init_keywords = { 'abstract' : types.BooleanType,
- 'cxx_namespace' : types.StringType,
'cxx_class' : types.StringType,
'cxx_type' : types.StringType,
'cxx_predecls' : types.ListType,
@@ -190,36 +189,31 @@
# the following is not true is when we define the SimObject
# class itself (in which case the multidicts have no parent).
if isinstance(base, MetaSimObject):
+ cls._base = base
cls._params.parent = base._params
cls._ports.parent = base._ports
cls._values.parent = base._values
cls._port_refs.parent = base._port_refs
# mark base as having been subclassed
base._instantiated = True
+ else:
+ cls._base = None
# default keyword values
if 'type' in cls._value_dict:
- _type = cls._value_dict['type']
if 'cxx_class' not in cls._value_dict:
- cls._value_dict['cxx_class'] = _type
+ cls._value_dict['cxx_class'] = cls._value_dict['type']
- namespace = cls._value_dict.get('cxx_namespace', None)
-
- _cxx_class = cls._value_dict['cxx_class']
- if 'cxx_type' not in cls._value_dict:
- t = _cxx_class + '*'
- if namespace:
- t = '%s::%s' % (namespace, t)
- cls._value_dict['cxx_type'] = t
+ cls._value_dict['cxx_type'] = '%s *' % cls._value_dict['cxx_class']
+
if 'cxx_predecls' not in cls._value_dict:
# A forward class declaration is sufficient since we are
# just declaring a pointer.
- decl = 'class %s;' % _cxx_class
- if namespace:
- namespaces = namespace.split('::')
- namespaces.reverse()
- for namespace in namespaces:
- decl = 'namespace %s { %s }' % (namespace, decl)
+ class_path = cls._value_dict['cxx_class'].split('::')
+ class_path.reverse()
+ decl = 'class %s;' % class_path[0]
+ for ns in class_path[1:]:
+ decl = 'namespace %s { %s }' % (ns, decl)
cls._value_dict['cxx_predecls'] = [decl]
if 'swig_predecls' not in cls._value_dict:
@@ -351,12 +345,6 @@
def __str__(cls):
return cls.__name__
- def get_base(cls):
- if str(cls) == 'SimObject':
- return None
-
- return cls.__bases__[0].type
-
def cxx_decl(cls):
code = "#ifndef __PARAMS__%s\n" % cls
code += "#define __PARAMS__%s\n\n" % cls
@@ -387,16 +375,15 @@
code += "\n".join(predecls2)
code += "\n\n";
- base = cls.get_base()
- if base:
- code += '#include "params/%s.hh"\n\n' % base
+ if cls._base:
+ code += '#include "params/%s.hh"\n\n' % cls._base.type
for ptype in ptypes:
if issubclass(ptype, Enum):
code += '#include "enums/%s.hh"\n' % ptype.__name__
code += "\n\n"
- code += cls.cxx_struct(base, params)
+ code += cls.cxx_struct(cls._base, params)
# close #ifndef __PARAMS__* guard
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