changeset dc073dc6358b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=dc073dc6358b
description:
X86: Rename the PC device to Pc.
diffstat:
3 files changed, 36 insertions(+), 36 deletions(-)
src/dev/x86/PC.py | 35 -----------------------------------
src/dev/x86/Pc.py | 35 +++++++++++++++++++++++++++++++++++
src/dev/x86/pc.hh | 2 +-
diffs (truncated from 311 to 300 lines):
diff -r 3d2451ebad92 -r dc073dc6358b configs/common/FSConfig.py
--- a/configs/common/FSConfig.py Sat Oct 11 02:21:44 2008 -0700
+++ b/configs/common/FSConfig.py Sat Oct 11 02:23:40 2008 -0700
@@ -180,7 +180,7 @@
self.bridge.side_b = self.membus.port
# Platform
- self.pc = PC()
+ self.pc = Pc()
self.pc.attachIO(self.iobus)
self.intrctrl = IntrControl()
diff -r 3d2451ebad92 -r dc073dc6358b src/dev/x86/PC.py
--- a/src/dev/x86/PC.py Sat Oct 11 02:21:44 2008 -0700
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,71 +0,0 @@
-# Copyright (c) 2008 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black
-
-from m5.params import *
-from m5.proxy import *
-
-from Device import IsaFake
-from Pci import PciConfigAll
-from Platform import Platform
-from SouthBridge import SouthBridge
-from Terminal import Terminal
-from Uart import Uart8250
-
-def x86IOAddress(port):
- IO_address_space_base = 0x8000000000000000
- return IO_address_space_base + port;
-
-class PC(Platform):
- type = 'PC'
- system = Param.System(Parent.any, "system")
-
- pciconfig = PciConfigAll()
-
- south_bridge = SouthBridge()
-
- # "Non-existant" port used for timing purposes by the linux kernel
- i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
-
- # Ports behind the pci config and data regsiters. These don't do anything,
- # but the linux kernel fiddles with them anway.
- behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8)
-
- # Serial port and terminal
- terminal = Terminal()
- com_1 = Uart8250()
- com_1.pio_addr = x86IOAddress(0x3f8)
- com_1.terminal = terminal
-
- def attachIO(self, bus):
- self.south_bridge.attachIO(bus)
- self.i_dont_exist.pio = bus.port
- self.behind_pci.pio = bus.port
- self.com_1.pio = bus.port
- self.pciconfig.pio = bus.default
- bus.responder_set = True
- bus.responder = self.pciconfig
diff -r 3d2451ebad92 -r dc073dc6358b src/dev/x86/Pc.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/dev/x86/Pc.py Sat Oct 11 02:23:40 2008 -0700
@@ -0,0 +1,71 @@
+# Copyright (c) 2008 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.params import *
+from m5.proxy import *
+
+from Device import IsaFake
+from Pci import PciConfigAll
+from Platform import Platform
+from SouthBridge import SouthBridge
+from Terminal import Terminal
+from Uart import Uart8250
+
+def x86IOAddress(port):
+ IO_address_space_base = 0x8000000000000000
+ return IO_address_space_base + port;
+
+class Pc(Platform):
+ type = 'Pc'
+ system = Param.System(Parent.any, "system")
+
+ pciconfig = PciConfigAll()
+
+ south_bridge = SouthBridge()
+
+ # "Non-existant" port used for timing purposes by the linux kernel
+ i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
+
+ # Ports behind the pci config and data regsiters. These don't do anything,
+ # but the linux kernel fiddles with them anway.
+ behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8)
+
+ # Serial port and terminal
+ terminal = Terminal()
+ com_1 = Uart8250()
+ com_1.pio_addr = x86IOAddress(0x3f8)
+ com_1.terminal = terminal
+
+ def attachIO(self, bus):
+ self.south_bridge.attachIO(bus)
+ self.i_dont_exist.pio = bus.port
+ self.behind_pci.pio = bus.port
+ self.com_1.pio = bus.port
+ self.pciconfig.pio = bus.default
+ bus.responder_set = True
+ bus.responder = self.pciconfig
diff -r 3d2451ebad92 -r dc073dc6358b src/dev/x86/SConscript
--- a/src/dev/x86/SConscript Sat Oct 11 02:21:44 2008 -0700
+++ b/src/dev/x86/SConscript Sat Oct 11 02:23:40 2008 -0700
@@ -31,7 +31,7 @@
Import('*')
if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
- SimObject('PC.py')
+ SimObject('Pc.py')
Source('pc.cc')
SimObject('SouthBridge.py')
diff -r 3d2451ebad92 -r dc073dc6358b src/dev/x86/pc.cc
--- a/src/dev/x86/pc.cc Sat Oct 11 02:21:44 2008 -0700
+++ b/src/dev/x86/pc.cc Sat Oct 11 02:23:40 2008 -0700
@@ -47,7 +47,7 @@
using namespace std;
using namespace TheISA;
-PC::PC(const Params *p)
+Pc::Pc(const Params *p)
: Platform(p), system(p->system)
{
southBridge = NULL;
@@ -56,7 +56,7 @@
}
void
-PC::init()
+Pc::init()
{
assert(southBridge);
I8254 & timer = *southBridge->pit;
@@ -70,40 +70,40 @@
}
Tick
-PC::intrFrequency()
+Pc::intrFrequency()
{
panic("Need implementation\n");
M5_DUMMY_RETURN
}
void
-PC::postConsoleInt()
+Pc::postConsoleInt()
{
warn_once("Don't know what interrupt to post for console.\n");
//panic("Need implementation\n");
}
void
-PC::clearConsoleInt()
+Pc::clearConsoleInt()
{
warn_once("Don't know what interrupt to clear for console.\n");
//panic("Need implementation\n");
}
void
-PC::postPciInt(int line)
+Pc::postPciInt(int line)
{
panic("Need implementation\n");
}
void
-PC::clearPciInt(int line)
+Pc::clearPciInt(int line)
{
panic("Need implementation\n");
}
Addr
-PC::pciToDma(Addr pciAddr) const
+Pc::pciToDma(Addr pciAddr) const
{
panic("Need implementation\n");
M5_DUMMY_RETURN
@@ -111,7 +111,7 @@
Addr
-PC::calcConfigAddr(int bus, int dev, int func)
+Pc::calcConfigAddr(int bus, int dev, int func)
{
assert(func < 8);
assert(dev < 32);
@@ -119,8 +119,8 @@
return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
}
-PC *
-PCParams::create()
+Pc *
+PcParams::create()
{
- return new PC(this);
+ return new Pc(this);
}
diff -r 3d2451ebad92 -r dc073dc6358b src/dev/x86/pc.hh
--- a/src/dev/x86/pc.hh Sat Oct 11 02:21:44 2008 -0700
+++ b/src/dev/x86/pc.hh Sat Oct 11 02:23:40 2008 -0700
@@ -38,13 +38,13 @@
#define __DEV_PC_HH__
#include "dev/platform.hh"
-#include "params/PC.hh"
+#include "params/Pc.hh"
class IdeController;
class System;
class SouthBridge;
-class PC : public Platform
+class Pc : public Platform
{
public:
/** Pointer to the system */
@@ -52,14 +52,14 @@
SouthBridge *southBridge;
public:
- typedef PCParams Params;
+ typedef PcParams Params;
/**
* Do platform initialization stuff
*/
void init();
- PC(const Params *p);
+ Pc(const Params *p);
/**
* Return the interrupting frequency to AlphaAccess
diff -r 3d2451ebad92 -r dc073dc6358b src/dev/x86/south_bridge.cc
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
